| /Linux-v6.1/arch/riscv/boot/dts/sifive/ |
| D | fu540-c000.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
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| D | fu740-c000.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu740-c000", "sifive,fu740";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
29 i-cache-sets = <128>;
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| /Linux-v6.1/arch/riscv/boot/dts/microchip/ |
| D | mpfs.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
20 i-cache-block-size = <64>;
21 i-cache-sets = <128>;
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| /Linux-v6.1/sound/pci/trident/ |
| D | trident_memory.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Trident 4DWave-NX memory page allocation (TLB area)
23 (trident)->tlb.entries[page] = cpu_to_le32((addr) & ~(SNDRV_TRIDENT_PAGE_SIZE-1))
25 (dma_addr_t)le32_to_cpu((trident->tlb.entries[page]) & ~(SNDRV_TRIDENT_PAGE_SIZE - 1))
28 /* page size == SNDRV_TRIDENT_PAGE_SIZE */
29 #define ALIGN_PAGE_SIZE PAGE_SIZE /* minimum page size for allocation */
31 /* fill TLB entrie(s) corresponding to page with ptr */
33 /* fill TLB entrie(s) corresponding to page with silence pointer */
34 #define set_silent_tlb(trident,page) __set_tlb_bus(trident, page, trident->tlb.silent_page->addr)
43 /* page size == SNDRV_TRIDENT_PAGE_SIZE x 2*/
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| /Linux-v6.1/arch/riscv/boot/dts/starfive/ |
| D | jh7100.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "sifive,u74-mc", "riscv";
23 d-cache-block-size = <64>;
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| /Linux-v6.1/arch/powerpc/mm/ |
| D | hugetlbpage.c | 2 * PPC Huge TLB Page Support for Kernel.
7 * Based on the IA-32 version:
23 #include <asm/tlb.h>
26 #include <asm/pte-walk.h>
33 #define PTE_T_ORDER (__builtin_ffs(sizeof(pte_basic_t)) - \
42 return __find_linux_pte(mm->pgd, addr, NULL, NULL); in huge_pte_offset()
51 int i; in __hugepte_alloc() local
56 num_hugepd = 1 << (pshift - pdshift); in __hugepte_alloc()
58 cachep = PGT_CACHE(pdshift - pshift); in __hugepte_alloc()
64 return -ENOMEM; in __hugepte_alloc()
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| /Linux-v6.1/arch/sparc/mm/ |
| D | hugetlbpage.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * SPARC64 Huge TLB page support.
17 #include <asm/tlb.h>
22 /* Slightly simplified from the non-hugepage variant because by
48 VM_BUG_ON(addr != -ENOMEM); in hugetlb_get_unmapped_area_bottomup()
64 struct mm_struct *mm = current->mm; in hugetlb_get_unmapped_area_topdown()
68 /* This should only ever run for 32-bit processes. */ in hugetlb_get_unmapped_area_topdown()
74 info.high_limit = mm->mmap_base; in hugetlb_get_unmapped_area_topdown()
81 * so fall back to the bottom-up function here. This scenario in hugetlb_get_unmapped_area_topdown()
86 VM_BUG_ON(addr != -ENOMEM); in hugetlb_get_unmapped_area_topdown()
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| /Linux-v6.1/arch/powerpc/boot/dts/ |
| D | microwatt.dts | 1 /dts-v1/;
4 #size-cells = <0x02>;
5 #address-cells = <0x02>;
6 model-name = "microwatt";
7 compatible = "microwatt-soc";
13 reserved-memory {
14 #size-cells = <0x02>;
15 #address-cells = <0x02>;
25 #size-cells = <0x00>;
26 #address-cells = <0x01>;
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| /Linux-v6.1/kernel/dma/ |
| D | swiotlb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * I/O TLBs (aka DMA address translation hardware).
9 * Copyright (C) 2000, 2003 Hewlett-Packard Co
10 * David Mosberger-Tang <davidm@hpl.hp.com>
12 * 03/05/07 davidm Switch from PCI-DMA to generic device DMA API.
14 * unnecessary i-cache flushing.
21 #define pr_fmt(fmt) "software IO TLB: " fmt
27 #include <linux/dma-direct.h>
28 #include <linux/dma-map-ops.h>
33 #include <linux/iommu-helper.h>
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| /Linux-v6.1/include/asm-generic/ |
| D | tlb.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* include/asm-generic/tlb.h
4 * Generic TLB shootdown code
32 * Generic MMU-gather implementation.
35 * correct and efficient ordering of freeing pages and TLB invalidations.
40 * 2) TLB invalidate page
49 * - tlb_gather_mmu() / tlb_gather_mmu_fullmm() / tlb_finish_mmu()
53 * Finish in particular will issue a (final) TLB invalidate and free
56 * - tlb_start_vma() / tlb_end_vma(); marks the start / end of a VMA
61 * - tlb_remove_table()
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| /Linux-v6.1/Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V bindings for 'cpus' DT nodes
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
29 - items:
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| /Linux-v6.1/arch/powerpc/mm/book3s64/ |
| D | hash_tlb.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * TLB and MMU hash table.
7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
25 #include <asm/tlb.h>
27 #include <asm/pte-walk.h>
49 int i, offset; in hpte_need_flush() local
51 i = batch->index; in hpte_need_flush()
54 * Get page size (maybe move back to caller). in hpte_need_flush()
57 * for SPEs, we obtain the page size from the slice, which thus in hpte_need_flush()
64 /* Mask the address for the correct page size */ in hpte_need_flush()
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| D | hash_native.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
23 #include <asm/tlb.h>
27 #include <asm/ppc-opcode.h>
28 #include <asm/feature-fixups.h>
30 #include <misc/cxl-base.h>
95 va &= ~((1ul << (64 - 52)) - 1); in ___tlbie()
100 : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206) in ___tlbie()
104 /* We need 14 to 14 + i bits of va */ in ___tlbie()
106 va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1); in ___tlbie()
119 : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206) in ___tlbie()
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| /Linux-v6.1/arch/nios2/kernel/ |
| D | cpuinfo.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
41 if (!of_property_read_bool(cpu, "altr,has-initda")) in setup_cpuinfo()
43 "hardware system to have more than 4-byte line data " in setup_cpuinfo()
46 cpuinfo.cpu_clock_freq = fcpu(cpu, "clock-frequency"); in setup_cpuinfo()
54 cpuinfo.has_div = of_property_read_bool(cpu, "altr,has-div"); in setup_cpuinfo()
55 cpuinfo.has_mul = of_property_read_bool(cpu, "altr,has-mul"); in setup_cpuinfo()
56 cpuinfo.has_mulx = of_property_read_bool(cpu, "altr,has-mulx"); in setup_cpuinfo()
57 cpuinfo.has_bmx = of_property_read_bool(cpu, "altr,has-bmx"); in setup_cpuinfo()
58 cpuinfo.has_cdx = of_property_read_bool(cpu, "altr,has-cdx"); in setup_cpuinfo()
59 cpuinfo.mmu = of_property_read_bool(cpu, "altr,has-mmu"); in setup_cpuinfo()
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| /Linux-v6.1/arch/powerpc/mm/nohash/ |
| D | 44x.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * -- paulus
11 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
27 #include <asm/code-patching.h>
32 /* Used by the 44x TLB replacement exception handler.
36 unsigned int tlb_44x_hwater = PPC44x_TLB_SIZE - 1 - PPC44x_EARLY_TLBS;
43 /* The TLB miss handlers hard codes the watermark in a cmpli in ppc44x_update_tlb_hwater()
46 * in the 2 TLB miss handlers when updating the value in ppc44x_update_tlb_hwater()
53 * "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 44x type MMU
57 unsigned int entry = tlb_44x_hwater--; in ppc44x_pin_tlb()
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| D | tlb.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * This file contains the routines for TLB flushing.
6 * this does -not- include 603 however which shares the implementation with
9 * -- BenH
15 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
39 #include <asm/tlb.h>
40 #include <asm/code-patching.h>
48 * This struct lists the sw-supported page sizes. The hardawre MMU may support
113 /* The variables below are currently only used on 64-bit Book3E
119 int mmu_pte_psize; /* Page size used for PTE pages */
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| /Linux-v6.1/Documentation/core-api/ |
| D | cachetlb.rst | 2 Cache and TLB Flushing Under Linux
7 This document describes the cache/tlb flushing interfaces called
17 thinking SMP cache/tlb flushing must be so inefficient, this is in
23 First, the TLB flushing interfaces, since they are the simplest. The
24 "TLB" is abstracted under Linux as something the cpu uses to cache
25 virtual-->physical address translations obtained from the software
27 possible for stale translations to exist in this "TLB" cache.
44 the TLB. After running, this interface must make sure that
47 there will be no entries in the TLB for 'mm'.
57 address translations from the TLB. After running, this
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| /Linux-v6.1/drivers/parisc/ |
| D | ccio-dma.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 ** ccio-dma.c:
4 ** DMA management routines for first generation cache-coherent machines.
5 ** Program U2/Uturn in "Virtual Mode" and use the I/O MMU.
9 ** (c) Copyright 2000 Hewlett-Packard Company
15 ** the I/O MMU - basically what x86 does.
17 ** Philipp Rumpf has a "Real Mode" driver for PCX-W machines at:
18 ** CVSROOT=:pserver:anonymous@198.186.203.37:/cvsroot/linux-parisc
19 ** cvs -z3 co linux/arch/parisc/kernel/dma-rm.c
21 ** I've rewritten his code to work under TPG's tree. See ccio-rm-dma.c.
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| /Linux-v6.1/arch/microblaze/include/asm/ |
| D | mmu.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2008-2009 PetaLogix
27 unsigned long w:1; /* Write-thru cache mode */
28 unsigned long i:1; /* Cache inhibited */ member
43 unsigned long t:1; /* Normal or I/O type */
46 unsigned long n:1; /* No-execute */
51 extern void _tlbie(unsigned long va); /* invalidate a TLB entry */
52 extern void _tlbia(void); /* invalidate all TLB entries */
55 * tlb_skip size stores actual number skipped TLBs from TLB0 - every directy TLB
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| /Linux-v6.1/arch/parisc/include/uapi/asm/ |
| D | pdc.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
14 #define PDC_BAD_PROC -1 /* Called non-existent procedure*/
15 #define PDC_BAD_OPTION -2 /* Called with non-existent option */
16 #define PDC_ERROR -3 /* Call could not complete without an error */
17 #define PDC_NE_MOD -5 /* Module not found */
18 #define PDC_NE_CELL_MOD -7 /* Cell module not found */
19 #define PDC_NE_BOOTDEV -9 /* Cannot locate a console device or boot device */
20 #define PDC_INVALID_ARG -10 /* Called with an invalid argument */
21 #define PDC_BUS_POW_WARN -12 /* Call could not complete in allowed power budget */
22 #define PDC_NOT_NARROW -17 /* Narrow mode not supported */
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| /Linux-v6.1/arch/powerpc/include/asm/nohash/32/ |
| D | pte-44x.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
9 * Because of the 3 word TLB entries to support 36-bit addressing,
11 * are easily loaded during exception processing. I decided to
14 * in as sensibly as they can be in the area below a 4KB page size
16 * ERPN fields in the TLB. -Matt
19 * easier to move into the TLB from the PTE. -BenH.
21 * Note that these bits preclude future use of a page size
25 * PPC 440 core has following TLB attribute fields;
29 * RPN................................. - - - - - - ERPN.......
33 * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR
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| D | pte-40x.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 * At present, all PowerPC 400-class processors share a similar TLB
9 * 64-entry, fully-associative TLB which is maintained totally under
11 * hardware-managed, 4-entry, fully-associative TLB which serves as a
12 * first level to the shared TLB. These two TLBs are known as the UTLB
19 * RPN..................... 0 0 EX WR ZSEL....... W I M G
23 * - bits 20 and 21 must be cleared, because we use 4k pages (40x can
26 * - We use only zones 0 (for kernel pages) and 1 (for user pages)
27 * of the 16 available. Bit 24-26 of the TLB are cleared in the TLB
30 * - PRESENT *must* be in the bottom two bits because swap cache
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| /Linux-v6.1/arch/parisc/kernel/ |
| D | cache.c | 6 * Copyright (C) 1999-2006 Helge Deller <deller@gmx.de> (07-13-1999)
10 * Cache and TLB management
43 void flush_data_cache_local(void *); /* flushes local data-cache only */
44 void flush_instruction_cache_local(void); /* flushes local code-cache only */
46 /* On some machines (i.e., ones with the Merced bus), there can be
48 * by software. We need a spinlock around all TLB flushes to ensure
109 test_bit(PG_dcache_dirty, &page->flags)) { in __update_cache()
111 clear_bit(PG_dcache_dirty, &page->flags); in __update_cache()
121 seq_printf(m, "I-cache\t\t: %ld KB\n", in show_cache_info()
124 snprintf(buf, 32, "%lu-way associative", cache_info.dc_loop); in show_cache_info()
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| /Linux-v6.1/arch/alpha/kernel/ |
| D | pci_iommu.c | 1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/dma-map-ops.h>
15 #include <linux/iommu-helper.h>
43 return (paddr >> (PAGE_SHIFT-1)) | 1; in mk_iommu_pte()
67 /* Note that the TLB lookup logic uses bitwise concatenation, in iommu_arena_new_node()
69 the size of the window. Retain the align parameter so that in iommu_arena_new_node()
70 particular systems can over-align the arena. */ in iommu_arena_new_node()
78 arena->ptes = memblock_alloc(mem_size, align); in iommu_arena_new_node()
79 if (!arena->ptes) in iommu_arena_new_node()
83 spin_lock_init(&arena->lock); in iommu_arena_new_node()
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| /Linux-v6.1/arch/x86/mm/ |
| D | pgtable.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <asm/tlb.h>
11 phys_addr_t physical_mask __ro_after_init = (1ULL << __PHYSICAL_MASK_SHIFT) - 1;
23 void paravirt_tlb_remove_table(struct mmu_gather *tlb, void *table) in paravirt_tlb_remove_table() argument
25 tlb_remove_page(tlb, table); in paravirt_tlb_remove_table()
39 return -EINVAL; in setup_userpte()
48 return -EINVAL; in setup_userpte()
53 void ___pte_free_tlb(struct mmu_gather *tlb, struct page *pte) in ___pte_free_tlb() argument
57 paravirt_tlb_remove_table(tlb, pte); in ___pte_free_tlb()
61 void ___pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd) in ___pmd_free_tlb() argument
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