6  * Copyright (C) 1999-2006 Helge Deller <deller@gmx.de> (07-13-1999)
10  * Cache and TLB management
43 void flush_data_cache_local(void *);  /* flushes local data-cache only */
44 void flush_instruction_cache_local(void); /* flushes local code-cache only */
46 /* On some machines (i.e., ones with the Merced bus), there can be
48  * by software. We need a spinlock around all TLB flushes to ensure
109 	    test_bit(PG_dcache_dirty, &page->flags)) {  in __update_cache()
111 		clear_bit(PG_dcache_dirty, &page->flags);  in __update_cache()
121 	seq_printf(m, "I-cache\t\t: %ld KB\n",   in show_cache_info()
124 		snprintf(buf, 32, "%lu-way associative", cache_info.dc_loop);  in show_cache_info()
125 	seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %s, alias=%d)\n",  in show_cache_info()
128 		(cache_info.dc_conf.cc_sh ? ", shared I/D":""),  in show_cache_info()
135 		cache_info.dt_conf.tc_sh ? " - shared with ITLB":""  in show_cache_info()
139 	/* BTLB - Block TLB */  in show_cache_info()
145 		"BTLB fix-entr.\t: %d instruction, %d data (%d combined)\n"  in show_cache_info()
146 		"BTLB var-entr.\t: %d instruction, %d data (%d combined)\n",  in show_cache_info()
226 	printk("D-TLB conf: sh %d page %d cst %d aid %d sr %d\n",  in parisc_cache_init()
233 	printk("I-TLB conf: sh %d page %d cst %d aid %d sr %d\n",  in parisc_cache_init()
244 			printk(KERN_WARNING "Unexpected TLB configuration. "  in parisc_cache_init()
245 			"Will flush I/D separately (could be optimized).\n");  in parisc_cache_init()
251 	 *	(1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift))  in parisc_cache_init()
253 	 * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023625.html  in parisc_cache_init()
254 	 * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023671.html  in parisc_cache_init()
271 		panic("SMP kernel required to avoid non-equivalent aliasing");  in parisc_cache_init()
322 	if (vma->vm_flags & VM_EXEC)  in __flush_cache_page()
346 	switch_mm_irqs_off(NULL, vma->vm_mm, NULL);  in flush_user_cache_page()
350 	if (vma->vm_flags & VM_EXEC)  in flush_user_cache_page()
370 	pgd_t *pgd = mm->pgd;  in get_ptep()
405 		set_bit(PG_dcache_dirty, &page->flags);  in flush_dcache_page()
414 	pgoff = page->index;  in flush_dcache_page()
424 	vma_interval_tree_foreach(mpnt, &mapping->i_mmap, pgoff, pgoff) {  in flush_dcache_page()
425 		offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;  in flush_dcache_page()
426 		addr = mpnt->vm_start + offset;  in flush_dcache_page()
430 			ptep = get_ptep(mpnt->vm_mm, addr);  in flush_dcache_page()
435 			 * The TLB is the engine of coherence on parisc:  in flush_dcache_page()
437 			 * with a TLB mapping, so here we kill the  in flush_dcache_page()
440 			 * the page is no-longer in the cache for any  in flush_dcache_page()
446 			if (old_addr == 0 || (old_addr & (SHM_COLOUR - 1))  in flush_dcache_page()
447 					!= (addr & (SHM_COLOUR - 1))) {  in flush_dcache_page()
453 				if (!(mpnt->vm_flags & VM_SHARED))  in flush_dcache_page()
457 						old_addr, addr, mpnt->vm_file);  in flush_dcache_page()
474 #define FLUSH_TLB_THRESHOLD (16*1024) /* 16 KiB minimum TLB threshold */
480 	unsigned long size;  in parisc_setup_cache_timing()  local
485 	alltime = mfctl(16) - alltime;  in parisc_setup_cache_timing()
487 	size = (unsigned long)(_end - _text);  in parisc_setup_cache_timing()
489 	flush_kernel_dcache_range((unsigned long)_text, size);  in parisc_setup_cache_timing()
490 	rangetime = mfctl(16) - rangetime;  in parisc_setup_cache_timing()
493 		alltime, size, rangetime);  in parisc_setup_cache_timing()
495 	threshold = L1_CACHE_ALIGN((unsigned long)((uint64_t)size * alltime / rangetime));  in parisc_setup_cache_timing()
508 	/* calculate TLB flush threshold */  in parisc_setup_cache_timing()
510 	/* On SMP machines, skip the TLB measure of kernel text which  in parisc_setup_cache_timing()
519 	size = (unsigned long)_end - (unsigned long)_text;  in parisc_setup_cache_timing()
522 	rangetime = mfctl(16) - rangetime;  in parisc_setup_cache_timing()
526 	alltime = mfctl(16) - alltime;  in parisc_setup_cache_timing()
528 	printk(KERN_INFO "Whole TLB flush %lu cycles, Range flush %lu bytes %lu cycles\n",  in parisc_setup_cache_timing()
529 		alltime, size, rangetime);  in parisc_setup_cache_timing()
531 	threshold = PAGE_ALIGN((num_online_cpus() * size * alltime) / rangetime);  in parisc_setup_cache_timing()
532 	printk(KERN_INFO "Calculated TLB flush threshold %lu KiB\n",  in parisc_setup_cache_timing()
541 	printk(KERN_INFO "TLB flush threshold set to %lu KiB\n",  in parisc_setup_cache_timing()
563 	pte_t *ptep = get_ptep(vma->vm_mm, vmaddr);  in flush_cache_page_if_present()
567 	 * a non-access TLB miss. Hopefully, the page has already been  in flush_cache_page_if_present()
612 	    end - start >= parisc_tlb_flush_threshold) {  in __flush_tlb_range()
617 	/* Purge TLB entries for small ranges using the pdtlb and  in __flush_tlb_range()
642 		ptep = get_ptep(vma->vm_mm, addr);  in flush_cache_pages()
665 		usize += vma->vm_end - vma->vm_start;  in mm_total_size()
694 		flush_cache_pages(vma, vma->vm_start, vma->vm_end);  in flush_cache_mm()
700 	    || end - start >= parisc_cache_flush_threshold) {  in flush_cache_range()
727 		if (vma->vm_flags & VM_SHARED)  in flush_anon_page()
740 void flush_kernel_vmap_range(void *vaddr, int size)  in flush_kernel_vmap_range()  argument
743 	unsigned long end = start + size;  in flush_kernel_vmap_range()
746 	    (unsigned long)size >= parisc_cache_flush_threshold) {  in flush_kernel_vmap_range()
757 void invalidate_kernel_vmap_range(void *vaddr, int size)  in invalidate_kernel_vmap_range()  argument
760 	unsigned long end = start + size;  in invalidate_kernel_vmap_range()
766 	    (unsigned long)size >= parisc_cache_flush_threshold) {  in invalidate_kernel_vmap_range()