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/Linux-v5.15/Documentation/devicetree/bindings/mmc/
Dmtk-sd.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chaotian Jing <chaotian.jing@mediatek.com>
11 - Wenbin Mei <wenbin.mei@mediatek.com>
14 - $ref: mmc-controller.yaml#
19 - enum:
20 - mediatek,mt2701-mmc
21 - mediatek,mt2712-mmc
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/Linux-v5.15/arch/arm64/boot/dts/mediatek/
Dmt8173-evb.dts1 // SPDX-License-Identifier: GPL-2.0-only
7 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
13 compatible = "mediatek,mt8173-evb", "mediatek,mt8173";
30 compatible = "hdmi-connector";
36 remote-endpoint = <&hdmi0_out>;
42 compatible = "linux,extcon-usb-gpio";
43 id-gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
47 compatible = "regulator-fixed";
48 regulator-name = "usb_vbus";
[all …]
Dmt8173-elm.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/regulator/dlg,da9211-regulator.h>
9 #include <dt-bindings/gpio/gpio.h>
25 compatible = "pwm-backlight";
27 power-supply = <&bl_fixed_reg>;
28 enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>;
30 pinctrl-names = "default";
31 pinctrl-0 = <&disp_pwm0_pins>;
[all …]
/Linux-v5.15/drivers/mmc/host/
Ddw_mmc-exynos.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include "dw_mmc-pltfm.h"
20 #include "dw_mmc-exynos.h"
22 /* Variations in Exynos specific dw-mshc controller */
52 .compatible = "samsung,exynos4210-dw-mshc",
55 .compatible = "samsung,exynos4412-dw-mshc",
58 .compatible = "samsung,exynos5250-dw-mshc",
61 .compatible = "samsung,exynos5420-dw-mshc",
64 .compatible = "samsung,exynos5420-dw-mshc-smu",
67 .compatible = "samsung,exynos7-dw-mshc",
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Dsdhci-xenon-phy.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Date: 2016-8-24
12 #include <linux/delay.h>
16 #include "sdhci-pltfm.h"
17 #include "sdhci-xenon.h"
200 static int xenon_alloc_emmc_phy(struct sdhci_host *host) in xenon_alloc_emmc_phy()
206 params = devm_kzalloc(mmc_dev(host->mmc), sizeof(*params), GFP_KERNEL); in xenon_alloc_emmc_phy()
208 return -ENOMEM; in xenon_alloc_emmc_phy()
210 priv->phy_params = params; in xenon_alloc_emmc_phy()
211 if (priv->phy_type == EMMC_5_0_PHY) in xenon_alloc_emmc_phy()
[all …]
Dsdhci-esdhc-imx.c1 // SPDX-License-Identifier: GPL-2.0
5 * derived from the OF-version.
14 #include <linux/delay.h>
23 #include <linux/mmc/slot-gpio.h>
28 #include "sdhci-pltfm.h"
29 #include "sdhci-esdhc.h"
81 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
125 * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
127 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
128 * Define this macro DMA error INT for fsl eSDHC
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Dmtk-sd.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015 MediaTek Inc.
9 #include <linux/delay.h>
10 #include <linux/dma-mapping.h>
33 #include <linux/mmc/slot-gpio.h>
40 /*--------------------------------------------------------------------------*/
42 /*--------------------------------------------------------------------------*/
49 /*--------------------------------------------------------------------------*/
51 /*--------------------------------------------------------------------------*/
88 /*--------------------------------------------------------------------------*/
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Dsunxi-mmc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
5 * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com>
6 * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch>
7 * (C) Copyright 2013-2014 David Lanzendörfer <david.lanzendoerfer@o2s.ch>
8 * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com>
13 #include <linux/clk/sunxi-ng.h>
14 #include <linux/delay.h>
16 #include <linux/dma-mapping.h>
27 #include <linux/mmc/slot-gpio.h>
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Drenesas_sdhi_core.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-19 Renesas Electronics Corporation
6 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
7 * Copyright (C) 2016-17 Horms Solutions, Simon Horman
13 * Copyright 2004-2005 Phil Blundell
14 * Copyright 2007-2008 OpenedHand Ltd.
22 #include <linux/delay.h>
28 #include <linux/mmc/slot-gpio.h>
32 #include <linux/pinctrl/pinctrl-state.h>
66 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width) in renesas_sdhi_sdbuf_width()
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Dsdhci-msm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
5 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
10 #include <linux/delay.h>
21 #include "sdhci-pltfm.h"
120 #define INVALID_TUNING_PHASE -1
134 /* Max load for eMMC Vdd-io supply */
138 msm_host->var_ops->msm_readl_relaxed(host, offset)
141 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
260 int pwr_irq; /* power irq */
[all …]
Dsdhci-xenon.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Date: 2016-8-24
15 #include <linux/delay.h>
22 #include "sdhci-pltfm.h"
23 #include "sdhci-xenon.h"
25 static int xenon_enable_internal_clk(struct sdhci_host *host) in xenon_enable_internal_clk()
42 dev_err(mmc_dev(host->mmc), "Internal clock never stabilised.\n"); in xenon_enable_internal_clk()
43 return -ETIMEDOUT; in xenon_enable_internal_clk()
51 /* Set SDCLK-off-while-idle */
92 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; in xenon_enable_sdhc()
[all …]
Dsdhci-of-esdhc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include <linux/delay.h>
22 #include <linux/dma-mapping.h>
26 #include "sdhci-pltfm.h"
27 #include "sdhci-esdhc.h"
35 const unsigned int sd_dflt_max_clk;
36 const unsigned int max_clk[MMC_TIMING_NUM];
65 { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk},
66 { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk},
67 { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk},
[all …]
Dsdhci.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
7 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
166 #define SDHCI_INT_ALL_MASK ((unsigned int)-1)
188 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
235 #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */
244 /* 4C-4F reserved for more max current */
251 /* 55-57 reserved */
256 /* 60-FB reserved */
264 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
[all …]
Dsdhci-tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/delay.h>
7 #include <linux/dma-mapping.h>
23 #include <linux/mmc/slot-gpio.h>
27 #include "sdhci-pltfm.h"
178 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) in tegra_sdhci_readw()
182 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_readw()
184 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && in tegra_sdhci_readw()
190 return readw(host->ioaddr + reg); in tegra_sdhci_readw()
193 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) in tegra_sdhci_writew()
[all …]
Dsdhci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
5 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
9 * - JMicron (hardware and technical support)
13 #include <linux/delay.h>
19 #include <linux/dma-mapping.h>
33 #include <linux/mmc/slot-gpio.h>
40 pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
43 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
47 static unsigned int debug_quirks = 0;
[all …]
Dmeson-gx-mmc.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
21 #include <linux/mmc/slot-gpio.h>
24 #include <linux/clk-provider.h>
31 #define DRIVER_NAME "meson-gx-mmc"
49 #define CLK_TX_DELAY_MASK(h) (h->data->tx_delay_mask)
50 #define CLK_RX_DELAY_MASK(h) (h->data->rx_delay_mask)
51 #define CLK_ALWAYS_ON(h) (h->data->always_on)
135 unsigned int tx_delay_mask;
[all …]
Ddw_mmc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include <linux/dma-mapping.h>
28 #include <linux/delay.h>
39 #include <linux/mmc/slot-gpio.h>
74 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
79 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
80 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
82 u32 des6; /* Lower 32-bits of Next Descriptor Address */
83 u32 des7; /* Upper 32-bits of Next Descriptor Address */
98 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
[all …]
/Linux-v5.15/include/linux/mmc/
Dhost.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 #include <linux/fault-inject.h>
17 #include <linux/dma-direction.h>
18 #include <linux/keyslot-manager.h>
21 unsigned int clock; /* clock rate */
23 unsigned int power_delay_ms; /* waiting for stable power */
106 int err);
110 int (*request_atomic)(struct mmc_host *host,
122 * ios->clock might be 0. For some controllers, setting 0Hz
132 * 1 for a read-only card
[all …]
/Linux-v5.15/arch/arm64/boot/dts/rockchip/
Drk3399-rock960.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include "rk3399-opp.dtsi"
18 sdio_pwrseq: sdio-pwrseq {
19 compatible = "mmc-pwrseq-simple";
21 clock-names = "ext_clock";
22 pinctrl-names = "default";
23 pinctrl-0 = <&wifi_enable_h>;
24 reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
27 vcc12v_dcin: vcc12v-dcin {
28 compatible = "regulator-fixed";
[all …]
Drk3399-rock-pi-4.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/input/linux-event-codes.h>
9 #include <dt-bindings/pwm/pwm.h>
11 #include "rk3399-opp.dtsi"
20 stdout-path = "serial2:1500000n8";
23 clkin_gmac: external-gmac-clock {
24 compatible = "fixed-clock";
25 clock-frequency = <125000000>;
26 clock-output-names = "clkin_gmac";
[all …]
Drk3399-gru.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
10 #include "rk3399-op1-opp.dtsi"
19 stdout-path = "serial2:115200n8";
28 * - Rails that only connect to the EC (or devices that the EC talks to)
30 * - Rails _are_ included if the rails go to the AP even if the AP
39 * - The EC controls the enable and the EC always enables a rail as
41 * - The rails are actually connected to each other by a jumper and
46 ppvar_sys: ppvar-sys {
[all …]