Lines Matching +full:hs400 +full:- +full:cmd +full:- +full:int +full:- +full:delay
1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include <linux/delay.h>
22 #include <linux/dma-mapping.h>
26 #include "sdhci-pltfm.h"
27 #include "sdhci-esdhc.h"
35 const unsigned int sd_dflt_max_clk;
36 const unsigned int max_clk[MMC_TIMING_NUM];
65 { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk},
66 { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk},
67 { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk},
68 { .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk},
69 { .compatible = "fsl,mpc8379-esdhc" },
70 { .compatible = "fsl,mpc8536-esdhc" },
88 unsigned int peripheral_clock;
94 * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register
109 int spec_reg, u32 value) in esdhc_readl_fixup()
124 if (esdhc->vendor_ver > VENDOR_V_22) { in esdhc_readl_fixup()
130 * The DAT[3:0] line signal levels and the CMD line signal level are in esdhc_readl_fixup()
162 (esdhc->quirk_ignore_data_inhibit == true)) { in esdhc_readl_fixup()
172 int spec_reg, u32 value) in esdhc_readw_fixup()
177 int shift = (spec_reg & 0x2) * 8; in esdhc_readw_fixup()
180 return pltfm_host->xfer_mode_shadow; in esdhc_readw_fixup()
186 /* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect in esdhc_readw_fixup()
190 (esdhc->quirk_incorrect_hostver)) in esdhc_readw_fixup()
196 int spec_reg, u32 value) in esdhc_readb_fixup()
200 int shift = (spec_reg & 0x3) * 8; in esdhc_readb_fixup()
219 * esdhc_write*_fixup - Fixup the SD spec register value so that it could be
235 int spec_reg, u32 value, u32 old_value) in esdhc_writel_fixup()
253 int spec_reg, u16 value, u32 old_value) in esdhc_writew_fixup()
256 int shift = (spec_reg & 0x2) * 8; in esdhc_writew_fixup()
265 pltfm_host->xfer_mode_shadow = value; in esdhc_writew_fixup()
268 ret = (value << 16) | pltfm_host->xfer_mode_shadow; in esdhc_writew_fixup()
278 * non-standard blksz of 4096 bytes that we don't support in esdhc_writew_fixup()
287 int spec_reg, u8 value, u32 old_value) in esdhc_writeb_fixup()
292 int shift = (spec_reg & 0x3) * 8; in esdhc_writeb_fixup()
309 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL) in esdhc_writeb_fixup()
328 static u32 esdhc_be_readl(struct sdhci_host *host, int reg) in esdhc_be_readl()
334 value = ioread32be(host->ioaddr + ESDHC_CAPABILITIES_1); in esdhc_be_readl()
336 value = ioread32be(host->ioaddr + reg); in esdhc_be_readl()
343 static u32 esdhc_le_readl(struct sdhci_host *host, int reg) in esdhc_le_readl()
349 value = ioread32(host->ioaddr + ESDHC_CAPABILITIES_1); in esdhc_le_readl()
351 value = ioread32(host->ioaddr + reg); in esdhc_le_readl()
358 static u16 esdhc_be_readw(struct sdhci_host *host, int reg) in esdhc_be_readw()
362 int base = reg & ~0x3; in esdhc_be_readw()
364 value = ioread32be(host->ioaddr + base); in esdhc_be_readw()
369 static u16 esdhc_le_readw(struct sdhci_host *host, int reg) in esdhc_le_readw()
373 int base = reg & ~0x3; in esdhc_le_readw()
375 value = ioread32(host->ioaddr + base); in esdhc_le_readw()
380 static u8 esdhc_be_readb(struct sdhci_host *host, int reg) in esdhc_be_readb()
384 int base = reg & ~0x3; in esdhc_be_readb()
386 value = ioread32be(host->ioaddr + base); in esdhc_be_readb()
391 static u8 esdhc_le_readb(struct sdhci_host *host, int reg) in esdhc_le_readb()
395 int base = reg & ~0x3; in esdhc_le_readb()
397 value = ioread32(host->ioaddr + base); in esdhc_le_readb()
402 static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg) in esdhc_be_writel()
407 iowrite32be(value, host->ioaddr + reg); in esdhc_be_writel()
410 static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg) in esdhc_le_writel()
415 iowrite32(value, host->ioaddr + reg); in esdhc_le_writel()
418 static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg) in esdhc_be_writew()
422 int base = reg & ~0x3; in esdhc_be_writew()
426 value = ioread32be(host->ioaddr + base); in esdhc_be_writew()
429 iowrite32be(ret, host->ioaddr + base); in esdhc_be_writew()
436 esdhc->in_sw_tuning) { in esdhc_be_writew()
439 iowrite32be(ret, host->ioaddr + base); in esdhc_be_writew()
444 static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg) in esdhc_le_writew()
448 int base = reg & ~0x3; in esdhc_le_writew()
452 value = ioread32(host->ioaddr + base); in esdhc_le_writew()
455 iowrite32(ret, host->ioaddr + base); in esdhc_le_writew()
462 esdhc->in_sw_tuning) { in esdhc_le_writew()
465 iowrite32(ret, host->ioaddr + base); in esdhc_le_writew()
470 static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg) in esdhc_be_writeb()
472 int base = reg & ~0x3; in esdhc_be_writeb()
476 value = ioread32be(host->ioaddr + base); in esdhc_be_writeb()
478 iowrite32be(ret, host->ioaddr + base); in esdhc_be_writeb()
481 static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg) in esdhc_le_writeb()
483 int base = reg & ~0x3; in esdhc_le_writeb()
487 value = ioread32(host->ioaddr + base); in esdhc_le_writeb()
489 iowrite32(ret, host->ioaddr + base); in esdhc_le_writeb()
497 * and re-issue the entire read transaction from beginning.
509 (esdhc->vendor_ver == VENDOR_V_23); in esdhc_of_adma_workaround()
513 host->data->error = 0; in esdhc_of_adma_workaround()
514 dmastart = sg_dma_address(host->data->sg); in esdhc_of_adma_workaround()
515 dmanow = dmastart + host->data->bytes_xfered; in esdhc_of_adma_workaround()
519 dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + in esdhc_of_adma_workaround()
521 host->data->bytes_xfered = dmanow - dmastart; in esdhc_of_adma_workaround()
525 static int esdhc_of_enable_dma(struct sdhci_host *host) in esdhc_of_enable_dma()
528 struct device *dev = mmc_dev(host->mmc); in esdhc_of_enable_dma()
530 if (of_device_is_compatible(dev->of_node, "fsl,ls1043a-esdhc") || in esdhc_of_enable_dma()
531 of_device_is_compatible(dev->of_node, "fsl,ls1046a-esdhc")) in esdhc_of_enable_dma()
536 if (of_dma_is_coherent(dev->of_node)) in esdhc_of_enable_dma()
545 static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host) in esdhc_of_get_max_clock()
550 if (esdhc->peripheral_clock) in esdhc_of_get_max_clock()
551 return esdhc->peripheral_clock; in esdhc_of_get_max_clock()
553 return pltfm_host->clock; in esdhc_of_get_max_clock()
556 static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host) in esdhc_of_get_min_clock()
560 unsigned int clock; in esdhc_of_get_min_clock()
562 if (esdhc->peripheral_clock) in esdhc_of_get_min_clock()
563 clock = esdhc->peripheral_clock; in esdhc_of_get_min_clock()
565 clock = pltfm_host->clock; in esdhc_of_get_min_clock()
582 if (esdhc->vendor_ver <= VENDOR_V_22) in esdhc_clock_enable()
600 while (esdhc->vendor_ver > VENDOR_V_22) { in esdhc_clock_enable()
607 mmc_hostname(host->mmc)); in esdhc_clock_enable()
633 mmc_hostname(host->mmc)); in esdhc_flush_async_fifo()
640 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock) in esdhc_of_set_clock()
644 unsigned int pre_div = 1, div = 1; in esdhc_of_set_clock()
645 unsigned int clock_fixup = 0; in esdhc_of_set_clock()
650 host->mmc->actual_clock = 0; in esdhc_of_set_clock()
656 if (esdhc->vendor_ver < VENDOR_V_23) in esdhc_of_set_clock()
660 if (host->mmc->card && mmc_card_sd(host->mmc->card) && in esdhc_of_set_clock()
661 esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY) in esdhc_of_set_clock()
662 clock_fixup = esdhc->clk_fixup->sd_dflt_max_clk; in esdhc_of_set_clock()
663 else if (esdhc->clk_fixup) in esdhc_of_set_clock()
664 clock_fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing]; in esdhc_of_set_clock()
670 while (host->max_clk / pre_div / 16 > clock_fixup && pre_div < 256) in esdhc_of_set_clock()
673 while (host->max_clk / pre_div / div > clock_fixup && div < 16) in esdhc_of_set_clock()
676 esdhc->div_ratio = pre_div * div; in esdhc_of_set_clock()
678 /* Limit clock division for HS400 200MHz clock for quirk. */ in esdhc_of_set_clock()
679 if (esdhc->quirk_limited_clk_division && in esdhc_of_set_clock()
681 (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 || in esdhc_of_set_clock()
682 host->flags & SDHCI_HS400_TUNING)) { in esdhc_of_set_clock()
683 if (esdhc->div_ratio <= 4) { in esdhc_of_set_clock()
686 } else if (esdhc->div_ratio <= 8) { in esdhc_of_set_clock()
689 } else if (esdhc->div_ratio <= 12) { in esdhc_of_set_clock()
694 mmc_hostname(host->mmc)); in esdhc_of_set_clock()
696 esdhc->div_ratio = pre_div * div; in esdhc_of_set_clock()
699 host->mmc->actual_clock = host->max_clk / esdhc->div_ratio; in esdhc_of_set_clock()
701 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", in esdhc_of_set_clock()
702 clock, host->mmc->actual_clock); in esdhc_of_set_clock()
706 div--; in esdhc_of_set_clock()
721 while (esdhc->vendor_ver > VENDOR_V_22) { in esdhc_of_set_clock()
728 mmc_hostname(host->mmc)); in esdhc_of_set_clock()
734 /* Additional setting for HS400. */ in esdhc_of_set_clock()
735 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && in esdhc_of_set_clock()
745 if (host->mmc->actual_clock == MMC_HS200_MAX_DTR) in esdhc_of_set_clock()
760 pr_err("%s: timeout for delay chain lock.\n", in esdhc_of_set_clock()
761 mmc_hostname(host->mmc)); in esdhc_of_set_clock()
772 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) in esdhc_pltfm_set_bus_width()
801 * Add delay to make sure all the DMA transfers are finished in esdhc_reset()
804 if (esdhc->quirk_delay_before_data_reset && in esdhc_reset()
806 (host->flags & SDHCI_REQ_USE_DMA)) in esdhc_reset()
810 * Save bus-width for eSDHC whose vendor version is 2.2 in esdhc_reset()
814 (esdhc->vendor_ver <= VENDOR_V_22)) { in esdhc_reset()
822 * Restore bus-width setting and interrupt registers for eSDHC in esdhc_reset()
826 (esdhc->vendor_ver <= VENDOR_V_22)) { in esdhc_reset()
832 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); in esdhc_reset()
833 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); in esdhc_reset()
841 (esdhc->spec_ver >= SDHCI_SPEC_300)) { in esdhc_reset()
850 if (esdhc->quirk_unreliable_pulse_detection) { in esdhc_reset()
864 { .compatible = "fsl,t1040-scfg", },
865 { .compatible = "fsl,ls1012a-scfg", },
866 { .compatible = "fsl,ls1046a-scfg", },
876 static int esdhc_signal_voltage_switch(struct mmc_host *mmc, in esdhc_signal_voltage_switch()
889 if (host->version < SDHCI_SPEC_300) in esdhc_signal_voltage_switch()
894 switch (ios->signal_voltage) { in esdhc_signal_voltage_switch()
997 if (esdhc->quirk_tuning_erratum_type1) { in esdhc_prepare_sw_tuning()
998 *window_start = 5 * esdhc->div_ratio; in esdhc_prepare_sw_tuning()
999 *window_end = 3 * esdhc->div_ratio; in esdhc_prepare_sw_tuning()
1010 /* If TBSTAT[15:8]-TBSTAT[7:0] > (4 * div_ratio) + 2 in esdhc_prepare_sw_tuning()
1011 * or TBSTAT[7:0]-TBSTAT[15:8] > (4 * div_ratio) + 2, in esdhc_prepare_sw_tuning()
1016 if (abs(start_ptr - end_ptr) > (4 * esdhc->div_ratio + 2)) { in esdhc_prepare_sw_tuning()
1017 *window_start = 8 * esdhc->div_ratio; in esdhc_prepare_sw_tuning()
1018 *window_end = 4 * esdhc->div_ratio; in esdhc_prepare_sw_tuning()
1020 *window_start = 5 * esdhc->div_ratio; in esdhc_prepare_sw_tuning()
1021 *window_end = 3 * esdhc->div_ratio; in esdhc_prepare_sw_tuning()
1025 static int esdhc_execute_sw_tuning(struct mmc_host *mmc, u32 opcode, in esdhc_execute_sw_tuning()
1032 int ret; in esdhc_execute_sw_tuning()
1046 esdhc->in_sw_tuning = true; in esdhc_execute_sw_tuning()
1048 esdhc->in_sw_tuning = false; in esdhc_execute_sw_tuning()
1052 static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) in esdhc_execute_tuning()
1058 int ret, retries = 1; in esdhc_execute_tuning()
1060 unsigned int clk; in esdhc_execute_tuning()
1066 clk = esdhc->peripheral_clock / 3; in esdhc_execute_tuning()
1067 if (host->clock > clk) in esdhc_execute_tuning()
1083 hs400_tuning = host->flags & SDHCI_HS400_TUNING; in esdhc_execute_tuning()
1086 if (esdhc->quirk_limited_clk_division && in esdhc_execute_tuning()
1088 esdhc_of_set_clock(host, host->clock); in esdhc_execute_tuning()
1104 if (esdhc->quirk_tuning_erratum_type2 && in esdhc_execute_tuning()
1105 !host->tuning_err) { in esdhc_execute_tuning()
1108 if (abs(window_start - window_end) > in esdhc_execute_tuning()
1109 (4 * esdhc->div_ratio + 2)) in esdhc_execute_tuning()
1110 host->tuning_err = -EAGAIN; in esdhc_execute_tuning()
1116 ret = host->tuning_err; in esdhc_execute_tuning()
1117 if (ret == -EAGAIN && in esdhc_execute_tuning()
1118 (esdhc->quirk_tuning_erratum_type1 || in esdhc_execute_tuning()
1119 esdhc->quirk_tuning_erratum_type2)) { in esdhc_execute_tuning()
1120 /* Recover HS400 tuning flag */ in esdhc_execute_tuning()
1122 host->flags |= SDHCI_HS400_TUNING; in esdhc_execute_tuning()
1135 ret = host->tuning_err; in esdhc_execute_tuning()
1136 if (ret == -EAGAIN && retries) { in esdhc_execute_tuning()
1137 /* Recover HS400 tuning flag */ in esdhc_execute_tuning()
1139 host->flags |= SDHCI_HS400_TUNING; in esdhc_execute_tuning()
1141 clk = host->max_clk / (esdhc->div_ratio + 1); in esdhc_execute_tuning()
1151 } while (retries--); in esdhc_execute_tuning()
1165 unsigned int timing) in esdhc_set_uhs_signaling()
1170 * There are specific registers setting for HS400 mode. in esdhc_set_uhs_signaling()
1171 * Clean all of them if controller is in HS400 mode to in esdhc_set_uhs_signaling()
1172 * exit HS400 mode before re-setting any speed mode. in esdhc_set_uhs_signaling()
1213 if (esdhc->quirk_trans_complete_erratum) { in esdhc_irq()
1229 static int esdhc_of_suspend(struct device *dev) in esdhc_of_suspend()
1235 if (host->tuning_mode != SDHCI_TUNING_MODE_3) in esdhc_of_suspend()
1236 mmc_retune_needed(host->mmc); in esdhc_of_suspend()
1241 static int esdhc_of_resume(struct device *dev) in esdhc_of_resume()
1244 int ret = sdhci_resume_host(host); in esdhc_of_resume()
1247 /* Isn't this already done by sdhci_resume_host() ? --rmk */ in esdhc_of_resume()
1346 esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >> in esdhc_init()
1348 esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK; in esdhc_init()
1350 esdhc->quirk_incorrect_hostver = true; in esdhc_init()
1352 esdhc->quirk_incorrect_hostver = false; in esdhc_init()
1355 esdhc->quirk_limited_clk_division = true; in esdhc_init()
1357 esdhc->quirk_limited_clk_division = false; in esdhc_init()
1360 esdhc->quirk_unreliable_pulse_detection = true; in esdhc_init()
1362 esdhc->quirk_unreliable_pulse_detection = false; in esdhc_init()
1364 match = of_match_node(sdhci_esdhc_of_match, pdev->dev.of_node); in esdhc_init()
1366 esdhc->clk_fixup = match->data; in esdhc_init()
1367 np = pdev->dev.of_node; in esdhc_init()
1369 if (of_device_is_compatible(np, "fsl,p2020-esdhc")) { in esdhc_init()
1370 esdhc->quirk_delay_before_data_reset = true; in esdhc_init()
1371 esdhc->quirk_trans_complete_erratum = true; in esdhc_init()
1377 * esdhc->peripheral_clock would be assigned with a value in esdhc_init()
1383 if (of_device_is_compatible(np, "fsl,ls1046a-esdhc") || in esdhc_init()
1384 of_device_is_compatible(np, "fsl,ls1028a-esdhc") || in esdhc_init()
1385 of_device_is_compatible(np, "fsl,ls1088a-esdhc")) in esdhc_init()
1386 esdhc->peripheral_clock = clk_get_rate(clk) / 2; in esdhc_init()
1388 esdhc->peripheral_clock = clk_get_rate(clk); in esdhc_init()
1400 if (esdhc->peripheral_clock) in esdhc_init()
1408 static int esdhc_hs400_prepare_ddr(struct mmc_host *mmc) in esdhc_hs400_prepare_ddr()
1414 static int sdhci_esdhc_probe(struct platform_device *pdev) in sdhci_esdhc_probe()
1420 int ret; in sdhci_esdhc_probe()
1422 np = pdev->dev.of_node; in sdhci_esdhc_probe()
1424 if (of_property_read_bool(np, "little-endian")) in sdhci_esdhc_probe()
1434 host->mmc_host_ops.start_signal_voltage_switch = in sdhci_esdhc_probe()
1436 host->mmc_host_ops.execute_tuning = esdhc_execute_tuning; in sdhci_esdhc_probe()
1437 host->mmc_host_ops.hs400_prepare_ddr = esdhc_hs400_prepare_ddr; in sdhci_esdhc_probe()
1438 host->tuning_delay = 1; in sdhci_esdhc_probe()
1447 esdhc->quirk_tuning_erratum_type1 = true; in sdhci_esdhc_probe()
1449 esdhc->quirk_tuning_erratum_type1 = false; in sdhci_esdhc_probe()
1452 esdhc->quirk_tuning_erratum_type2 = true; in sdhci_esdhc_probe()
1454 esdhc->quirk_tuning_erratum_type2 = false; in sdhci_esdhc_probe()
1456 if (esdhc->vendor_ver == VENDOR_V_22) in sdhci_esdhc_probe()
1457 host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; in sdhci_esdhc_probe()
1459 if (esdhc->vendor_ver > VENDOR_V_22) in sdhci_esdhc_probe()
1460 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; in sdhci_esdhc_probe()
1462 if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc")) { in sdhci_esdhc_probe()
1463 host->quirks |= SDHCI_QUIRK_RESET_AFTER_REQUEST; in sdhci_esdhc_probe()
1464 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; in sdhci_esdhc_probe()
1467 if (of_device_is_compatible(np, "fsl,p5040-esdhc") || in sdhci_esdhc_probe()
1468 of_device_is_compatible(np, "fsl,p5020-esdhc") || in sdhci_esdhc_probe()
1469 of_device_is_compatible(np, "fsl,p4080-esdhc") || in sdhci_esdhc_probe()
1470 of_device_is_compatible(np, "fsl,p1020-esdhc") || in sdhci_esdhc_probe()
1471 of_device_is_compatible(np, "fsl,t1040-esdhc")) in sdhci_esdhc_probe()
1472 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; in sdhci_esdhc_probe()
1474 if (of_device_is_compatible(np, "fsl,ls1021a-esdhc")) in sdhci_esdhc_probe()
1475 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; in sdhci_esdhc_probe()
1477 esdhc->quirk_ignore_data_inhibit = false; in sdhci_esdhc_probe()
1478 if (of_device_is_compatible(np, "fsl,p2020-esdhc")) { in sdhci_esdhc_probe()
1480 * Freescale messed up with P2020 as it has a non-standard in sdhci_esdhc_probe()
1483 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL; in sdhci_esdhc_probe()
1484 esdhc->quirk_ignore_data_inhibit = true; in sdhci_esdhc_probe()
1488 ret = mmc_of_parse(host->mmc); in sdhci_esdhc_probe()
1492 mmc_of_parse_voltage(host->mmc, &host->ocr_mask); in sdhci_esdhc_probe()
1506 .name = "sdhci-esdhc",