Lines Matching +full:hs400 +full:- +full:cmd +full:- +full:int +full:- +full:delay
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
7 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
166 #define SDHCI_INT_ALL_MASK ((unsigned int)-1)
188 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
235 #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */
244 /* 4C-4F reserved for more max current */
251 /* 55-57 reserved */
256 /* 60-FB reserved */
264 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
294 #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
296 /* ADMA2 32-bit DMA descriptor size */
299 /* ADMA2 32-bit descriptor */
301 __le16 cmd; member
308 #define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1)
312 * alignment for the descriptor table even in 32-bit DMA mode. Memory
318 * ADMA2 64-bit DMA descriptor size
320 * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit
322 * register, 128-bit Descriptor will be selected.
324 #define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12)
327 * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
331 __le16 cmd; member
368 unsigned int quirks; /* Deviations from spec. */
384 /* Controller can only DMA from 32-bit aligned addresses */
398 /* Controller does not provide transfer-complete interrupt when not busy */
402 /* Controller reports inverted write-protect state */
412 /* Controller cannot do multi-block transfers */
414 /* Controller can only handle 1-bit data transfers */
416 /* Controller needs 10ms delay between applying power and clock */
428 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */
432 /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
435 unsigned int quirks2; /* More deviations from spec. */
443 /* Controller has a non-standard host control register */
451 /* Controller does not support 64-bit DMA */
453 /* need clear transfer mode register before send cmd */
455 /* Capability register bit-63 indicates HS400 support */
473 * 32-bit block count may not support eMMC where upper bits of CMD23 are used
474 * for other purposes. Consequently we support 16-bit block count by default.
475 * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit
480 int irq; /* Device IRQ */
485 unsigned int bounce_buffer_size;
501 int flags; /* Host attributes */
510 #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */
511 #define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */
516 unsigned int version; /* SDHCI spec. version */
518 unsigned int max_clk; /* Max possible freq (MHz) */
519 unsigned int timeout_clk; /* Timeout freq (KHz) */
521 unsigned int clk_mul; /* Clock Muliplier value */
523 unsigned int clock; /* Current clock (MHz) */
529 bool pending_reset; /* Cmd/data reset is pending */
536 struct mmc_command *cmd; /* Current command */ member
540 unsigned int data_early:1; /* Data finished before cmd */
543 unsigned int blocks; /* remaining PIO blocks */
545 int sg_count; /* Mapped sg entries */
556 unsigned int desc_sz; /* ADMA current descriptor size */
557 unsigned int alloc_desc_sz; /* ADMA descr. max size host supports */
575 unsigned int ocr_avail_sdio; /* OCR bit masks */
576 unsigned int ocr_avail_sd;
577 unsigned int ocr_avail_mmc;
592 unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */
594 unsigned int tuning_count; /* Timer count for re-tuning */
595 unsigned int tuning_mode; /* Re-tuning mode supported by host */
596 unsigned int tuning_err; /* Error code for re-tuning */
600 /* Delay (ms) between tuning commands */
601 int tuning_delay;
602 int tuning_loop_count;
617 u32 (*read_l)(struct sdhci_host *host, int reg);
618 u16 (*read_w)(struct sdhci_host *host, int reg);
619 u8 (*read_b)(struct sdhci_host *host, int reg);
620 void (*write_l)(struct sdhci_host *host, u32 val, int reg);
621 void (*write_w)(struct sdhci_host *host, u16 val, int reg);
622 void (*write_b)(struct sdhci_host *host, u8 val, int reg);
625 void (*set_clock)(struct sdhci_host *host, unsigned int clock);
631 int (*set_dma_mask)(struct sdhci_host *host);
632 int (*enable_dma)(struct sdhci_host *host);
633 unsigned int (*get_max_clock)(struct sdhci_host *host);
634 unsigned int (*get_min_clock)(struct sdhci_host *host);
636 unsigned int (*get_timeout_clock)(struct sdhci_host *host);
637 unsigned int (*get_max_timeout_count)(struct sdhci_host *host);
639 struct mmc_command *cmd);
640 void (*set_bus_width)(struct sdhci_host *host, int width);
643 unsigned int (*get_ro)(struct sdhci_host *host);
645 int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode);
646 void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
652 dma_addr_t addr, int len, unsigned int cmd);
655 unsigned int length);
663 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) in sdhci_writel()
665 if (unlikely(host->ops->write_l)) in sdhci_writel()
666 host->ops->write_l(host, val, reg); in sdhci_writel()
668 writel(val, host->ioaddr + reg); in sdhci_writel()
671 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) in sdhci_writew()
673 if (unlikely(host->ops->write_w)) in sdhci_writew()
674 host->ops->write_w(host, val, reg); in sdhci_writew()
676 writew(val, host->ioaddr + reg); in sdhci_writew()
679 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) in sdhci_writeb()
681 if (unlikely(host->ops->write_b)) in sdhci_writeb()
682 host->ops->write_b(host, val, reg); in sdhci_writeb()
684 writeb(val, host->ioaddr + reg); in sdhci_writeb()
687 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl()
689 if (unlikely(host->ops->read_l)) in sdhci_readl()
690 return host->ops->read_l(host, reg); in sdhci_readl()
692 return readl(host->ioaddr + reg); in sdhci_readl()
695 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) in sdhci_readw()
697 if (unlikely(host->ops->read_w)) in sdhci_readw()
698 return host->ops->read_w(host, reg); in sdhci_readw()
700 return readw(host->ioaddr + reg); in sdhci_readw()
703 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) in sdhci_readb()
705 if (unlikely(host->ops->read_b)) in sdhci_readb()
706 return host->ops->read_b(host, reg); in sdhci_readb()
708 return readb(host->ioaddr + reg); in sdhci_readb()
713 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) in sdhci_writel()
715 writel(val, host->ioaddr + reg); in sdhci_writel()
718 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) in sdhci_writew()
720 writew(val, host->ioaddr + reg); in sdhci_writew()
723 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) in sdhci_writeb()
725 writeb(val, host->ioaddr + reg); in sdhci_writeb()
728 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl()
730 return readl(host->ioaddr + reg); in sdhci_readl()
733 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) in sdhci_readw()
735 return readw(host->ioaddr + reg); in sdhci_readw()
738 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) in sdhci_readb()
740 return readb(host->ioaddr + reg); in sdhci_readb()
750 return host->private; in sdhci_priv()
756 int sdhci_setup_host(struct sdhci_host *host);
758 int __sdhci_add_host(struct sdhci_host *host);
759 int sdhci_add_host(struct sdhci_host *host);
760 void sdhci_remove_host(struct sdhci_host *host, int dead);
767 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
768 unsigned int *actual_clock);
769 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
779 int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq);
780 void sdhci_set_bus_width(struct sdhci_host *host, int width);
783 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
785 int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
787 void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable);
789 dma_addr_t addr, int len, unsigned int cmd);
792 int sdhci_suspend_host(struct sdhci_host *host);
793 int sdhci_resume_host(struct sdhci_host *host);
794 int sdhci_runtime_suspend_host(struct sdhci_host *host);
795 int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset);
800 bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
801 int *data_error);
813 void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd);