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/Linux-v5.10/drivers/cpufreq/
Ds3c2412-cpufreq.c44 static struct clk *hclk; variable
52 unsigned long hclk, fclk, armclk, armdiv_clk; in s3c2412_cpufreq_calcdivs() local
57 hclk_max = cfg->max.hclk; in s3c2412_cpufreq_calcdivs()
59 /* We can't run hclk above armclk as at the best we have to in s3c2412_cpufreq_calcdivs()
60 * have armclk and hclk in dvs mode. */ in s3c2412_cpufreq_calcdivs()
69 cfg->freq.hclk, cfg->freq.pclk); in s3c2412_cpufreq_calcdivs()
85 cfg->freq.hclk = hclk = armdiv_clk / hdiv; in s3c2412_cpufreq_calcdivs()
91 cfg->freq.armclk = dvs ? hclk : armdiv_clk; in s3c2412_cpufreq_calcdivs()
93 s3c_freq_dbg("%s: armclk %lu, hclk %lu, armdiv %d, hdiv %d, dvs %d\n", in s3c2412_cpufreq_calcdivs()
94 __func__, armclk, hclk, armdiv, hdiv, cfg->divs.dvs); in s3c2412_cpufreq_calcdivs()
[all …]
Ds3c2440-cpufreq.c47 static struct clk *hclk; variable
70 unsigned long hclk, fclk, armclk; in s3c2440_cpufreq_calcdivs() local
75 hclk_max = cfg->max.hclk; in s3c2440_cpufreq_calcdivs()
77 s3c_freq_dbg("%s: fclk is %lu, armclk %lu, max hclk %lu\n", in s3c2440_cpufreq_calcdivs()
85 /* if we are in DVS, we need HCLK to be <= ARMCLK */ in s3c2440_cpufreq_calcdivs()
93 hclk = (fclk / hdiv); in s3c2440_cpufreq_calcdivs()
94 if (hclk <= hclk_max || within_khz(hclk, hclk_max)) in s3c2440_cpufreq_calcdivs()
98 s3c_freq_dbg("%s: hclk %lu, div %d\n", __func__, hclk, hdiv); in s3c2440_cpufreq_calcdivs()
103 pdiv = (hclk > cfg->max.pclk) ? 2 : 1; in s3c2440_cpufreq_calcdivs()
105 if ((hclk / pdiv) > cfg->max.pclk) in s3c2440_cpufreq_calcdivs()
[all …]
Ds3c2410-cpufreq.c45 unsigned long hclk, fclk, pclk; in s3c2410_cpufreq_calcdivs() local
50 hclk_max = cfg->max.hclk; in s3c2410_cpufreq_calcdivs()
54 s3c_freq_dbg("%s: fclk is %lu, max hclk %lu\n", in s3c2410_cpufreq_calcdivs()
57 hdiv = (fclk > cfg->max.hclk) ? 2 : 1; in s3c2410_cpufreq_calcdivs()
58 hclk = fclk / hdiv; in s3c2410_cpufreq_calcdivs()
60 if (hclk > cfg->max.hclk) { in s3c2410_cpufreq_calcdivs()
61 s3c_freq_dbg("%s: hclk too big\n", __func__); in s3c2410_cpufreq_calcdivs()
65 pdiv = (hclk > cfg->max.pclk) ? 2 : 1; in s3c2410_cpufreq_calcdivs()
66 pclk = hclk / pdiv; in s3c2410_cpufreq_calcdivs()
85 .hclk = 100000000,
[all …]
Ds3c2416-cpufreq.c27 struct clk *hclk; member
130 pr_debug("cpufreq: switching armclk to hclk (%lukHz)\n", in s3c2416_cpufreq_enter_dvs()
131 clk_get_rate(s3c_freq->hclk) / 1000); in s3c2416_cpufreq_enter_dvs()
132 ret = clk_set_parent(s3c_freq->armclk, s3c_freq->hclk); in s3c2416_cpufreq_enter_dvs()
134 pr_err("cpufreq: Failed to switch armclk to hclk: %d\n", ret); in s3c2416_cpufreq_enter_dvs()
188 /* force armdiv to hclk frequency for transition from dvs*/ in s3c2416_cpufreq_leave_dvs()
189 if (clk_get_rate(s3c_freq->armdiv) > clk_get_rate(s3c_freq->hclk)) { in s3c2416_cpufreq_leave_dvs()
190 pr_debug("cpufreq: force armdiv to hclk frequency (%lukHz)\n", in s3c2416_cpufreq_leave_dvs()
191 clk_get_rate(s3c_freq->hclk) / 1000); in s3c2416_cpufreq_leave_dvs()
193 clk_get_rate(s3c_freq->hclk) / 1000); in s3c2416_cpufreq_leave_dvs()
[all …]
Ds3c24xx-cpufreq.c60 unsigned long fclk, pclk, hclk, armclk; in s3c_cpufreq_getcur() local
63 cfg->freq.hclk = hclk = clk_get_rate(clk_hclk); in s3c_cpufreq_getcur()
70 cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10); in s3c_cpufreq_getcur()
72 cfg->divs.h_divisor = fclk / hclk; in s3c_cpufreq_getcur()
81 cfg->freq.hclk = pll / cfg->divs.h_divisor; in s3c_cpufreq_calc()
84 /* convert hclk into 10ths of nanoseconds for io calcs */ in s3c_cpufreq_calc()
85 cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10); in s3c_cpufreq_calc()
101 cfg->freq.hclk, cfg->divs.h_divisor, in s3c_cpufreq_show()
183 if (cpu_new.freq.hclk != cpu_cur.freq.hclk) { in s3c_cpufreq_settarget()
206 s3c_cpufreq_updateclk(clk_hclk, cpu_new.freq.hclk); in s3c_cpufreq_settarget()
[all …]
Ds3c24xx-cpufreq-debugfs.c33 f->fclk, f->hclk, f->pclk, f->armclk); in show_max()
76 seq_printf(seq, " HCLK %ld Hz (%lu.%lu ns)\n", in info_show()
77 cfg->freq.hclk, print_ns(cfg->freq.hclk_tns)); in info_show()
78 seq_printf(seq, " PCLK %ld Hz\n", cfg->freq.hclk); in info_show()
122 seq_printf(seq, "hclk period is %lu.%lu ns\n", print_ns(cfg->freq.hclk_tns)); in io_show()
/Linux-v5.10/arch/arm/mach-s3c/
Diotiming-s3c2410.c78 * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
81 * HCLK.
94 * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
107 s3c_freq_iodbg("%s: cyc=%d, hclk=%lu, shift=%d => div %d\n", in calc_0124()
132 static int calc_tacp(unsigned int cyc, unsigned long hclk, unsigned long *v) in calc_tacp() argument
142 * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
155 s3c_freq_iodbg("%s: cyc=%u, nwait=%d, hclk=%lu => div=%u\n", in calc_tacc()
216 unsigned long hclk = cfg->freq.hclk_tns; in s3c2410_calc_bank() local
230 ret = calc_0124(bt->tacs, hclk, &res, S3C2410_BANKCON_Tacs_SHIFT); in s3c2410_calc_bank()
231 ret |= calc_0124(bt->tcos, hclk, &res, S3C2410_BANKCON_Tcos_SHIFT); in s3c2410_calc_bank()
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Diotiming-s3c2412.c94 unsigned int hclk = cfg->freq.hclk_tns; in s3c2412_calc_bank() local
97 bt->smbidcyr = calc_timing(bt->idcy, hclk, &err); in s3c2412_calc_bank()
98 bt->smbwstrd = calc_timing(bt->wstrd, hclk, &err); in s3c2412_calc_bank()
99 bt->smbwstwr = calc_timing(bt->wstwr, hclk, &err); in s3c2412_calc_bank()
100 bt->smbwstoen = calc_timing(bt->wstoen, hclk, &err); in s3c2412_calc_bank()
101 bt->smbwstwen = calc_timing(bt->wstwen, hclk, &err); in s3c2412_calc_bank()
102 bt->smbwstbrd = calc_timing(bt->wstbrd, hclk, &err); in s3c2412_calc_bank()
267 * This should work for HCLK up to 133MHz and refresh period up in s3c2412_cpufreq_setrefresh()
271 refresh = (cfg->freq.hclk / 100) * (board->refresh / 10); in s3c2412_cpufreq_setrefresh()
/Linux-v5.10/drivers/clk/samsung/
Dclk-s3c64xx.c163 DIV(HCLK, "hclk", "hclkx2", CLK_DIV0, 8, 1),
191 DIV(DOUT_FIMC, "dout_fimc", "hclk", CLK_DIV1, 24, 4),
197 GATE_BUS(HCLK_UHOST, "hclk_uhost", "hclk", HCLK_GATE, 29),
198 GATE_BUS(HCLK_SECUR, "hclk_secur", "hclk", HCLK_GATE, 28),
199 GATE_BUS(HCLK_SDMA1, "hclk_sdma1", "hclk", HCLK_GATE, 27),
200 GATE_BUS(HCLK_SDMA0, "hclk_sdma0", "hclk", HCLK_GATE, 26),
201 GATE_ON(HCLK_DDR1, "hclk_ddr1", "hclk", HCLK_GATE, 24),
202 GATE_BUS(HCLK_USB, "hclk_usb", "hclk", HCLK_GATE, 20),
203 GATE_BUS(HCLK_HSMMC2, "hclk_hsmmc2", "hclk", HCLK_GATE, 19),
204 GATE_BUS(HCLK_HSMMC1, "hclk_hsmmc1", "hclk", HCLK_GATE, 18),
[all …]
Dclk-s3c2443.c67 PNAME(armclk_p) = { "armdiv" , "hclk" };
101 DIV_T(HCLK, "hclk", "prediv", CLKDIV0, 0, 2, hclk_d),
102 DIV(PCLK, "pclk", "hclk", CLKDIV0, 2, 1),
118 GATE(HCLK_DRAM, "dram", "hclk", HCLKCON, 19, CLK_IGNORE_UNUSED, 0),
119 GATE(HCLK_SSMC, "ssmc", "hclk", HCLKCON, 18, CLK_IGNORE_UNUSED, 0),
120 GATE(HCLK_HSMMC1, "hsmmc1", "hclk", HCLKCON, 16, 0, 0),
121 GATE(HCLK_USBD, "usb-device", "hclk", HCLKCON, 12, 0, 0),
122 GATE(HCLK_USBH, "usb-host", "hclk", HCLKCON, 11, 0, 0),
123 GATE(HCLK_LCD, "lcd", "hclk", HCLKCON, 9, 0, 0),
124 GATE(HCLK_DMA5, "dma5", "hclk", HCLKCON, 5, CLK_IGNORE_UNUSED, 0),
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Dclk-s3c2412.c61 DIV(0, "div_hclk_half", "hclk", CLKDIVN, 5, 1),
63 DIV(PCLK, "pclk", "hclk", CLKDIVN, 2, 1),
64 DIV(HCLK, "hclk", "armdiv", CLKDIVN, 0, 2),
68 FFACTOR(0, "ff_hclk", "hclk", 2, 1, CLK_SET_RATE_PARENT),
78 PNAME(camclk_p) = { "usysclk", "hclk" };
79 PNAME(usbclk_p) = { "usysclk", "hclk" };
85 PNAME(armclk_p) = { "armdiv", "hclk" };
126 GATE(HCLK_SDRAM, "sdram", "hclk", CLKCON, 8, CLK_IGNORE_UNUSED, 0),
127 GATE(HCLK_USBH, "usb-host", "hclk", CLKCON, 6, 0, 0),
128 GATE(HCLK_LCD, "lcd", "hclk", CLKCON, 5, 0, 0),
[all …]
Dclk-s5pv210-audss.c71 struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio; in s5pv210_audss_clk_probe() local
90 hclk = devm_clk_get(&pdev->dev, "hclk"); in s5pv210_audss_clk_probe()
91 if (IS_ERR(hclk)) { in s5pv210_audss_clk_probe()
92 dev_err(&pdev->dev, "failed to get hclk clock\n"); in s5pv210_audss_clk_probe()
93 return PTR_ERR(hclk); in s5pv210_audss_clk_probe()
144 hclk_p = __clk_get_name(hclk); in s5pv210_audss_clk_probe()
Dclk-s3c2410.c74 DIV(PCLK, "pclk", "hclk", CLKDIVN, 0, 1),
89 GATE(HCLK_USBD, "usb-device", "hclk", CLKCON, 7, 0, 0),
90 GATE(HCLK_USBH, "usb-host", "hclk", CLKCON, 6, 0, 0),
91 GATE(HCLK_LCD, "lcd", "hclk", CLKCON, 5, 0, 0),
92 GATE(HCLK_NAND, "nand", "hclk", CLKCON, 4, 0, 0),
108 ALIAS(HCLK, NULL, "hclk"),
162 DIV(HCLK, "hclk", "mpll", CLKDIVN, 1, 1),
228 PNAME(armclk_p) = { "fclk", "hclk" };
231 MUX(HCLK, "hclk", hclk_p, CLKDIVN, 1, 2),
261 GATE(HCLK_CAM, "cam", "hclk", CLKCON, 19, 0, 0),
/Linux-v5.10/drivers/clk/imx/
Dclk-imx1.c23 static const char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m",
53 clk[IMX1_CLK_HCLK] = imx_clk_divider("hclk", "spll_gate", CCM_CSCR, 10, 4); in mx1_clocks_init_dt()
59 clk[IMX1_CLK_UART3_GATE] = imx_clk_gate("uart3_gate", "hclk", SCM_GCCR, 6); in mx1_clocks_init_dt()
60 clk[IMX1_CLK_SSI2_GATE] = imx_clk_gate("ssi2_gate", "hclk", SCM_GCCR, 5); in mx1_clocks_init_dt()
61 clk[IMX1_CLK_BROM_GATE] = imx_clk_gate("brom_gate", "hclk", SCM_GCCR, 4); in mx1_clocks_init_dt()
62 clk[IMX1_CLK_DMA_GATE] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 3); in mx1_clocks_init_dt()
63 clk[IMX1_CLK_CSI_GATE] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2); in mx1_clocks_init_dt()
64 clk[IMX1_CLK_MMA_GATE] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1); in mx1_clocks_init_dt()
/Linux-v5.10/drivers/clk/
Dclk-stm32h7.c73 "hclk", "pll1_q", "pll2_r", "per_ck" };
76 "hclk", "pll1_q", "pll2_r", "per_ck" };
517 hws[HCLK] = clk_hw_register_divider_table(NULL, "hclk", "d1cpre", in register_core_and_bus_clocks()
527 hws[PCLK3] = clk_hw_register_divider_table(NULL, "pclk3", "hclk", 0, in register_core_and_bus_clocks()
533 hws[PCLK1] = clk_hw_register_divider_table(NULL, "pclk1", "hclk", 0, in register_core_and_bus_clocks()
542 hws[PCLK2] = clk_hw_register_divider_table(NULL, "pclk2", "hclk", 0, in register_core_and_bus_clocks()
551 hws[PCLK4] = clk_hw_register_divider_table(NULL, "pclk4", "hclk", 0, in register_core_and_bus_clocks()
999 PER_CLK(RCC_AHB3ENR, 31, "d1sram1", "hclk"),
1000 PER_CLK(RCC_AHB3ENR, 30, "itcm", "hclk"),
1001 PER_CLK(RCC_AHB3ENR, 29, "dtcm2", "hclk"),
[all …]
/Linux-v5.10/drivers/net/ethernet/cadence/
Dmacb_pci.c69 plat_data.hclk = clk_register_fixed_rate(&pdev->dev, "hclk", NULL, 0, in macb_probe()
71 if (IS_ERR(plat_data.hclk)) { in macb_probe()
72 err = PTR_ERR(plat_data.hclk); in macb_probe()
100 clk_unregister(plat_data.hclk); in macb_probe()
116 clk_unregister(plat_data->hclk); in macb_remove()
/Linux-v5.10/Documentation/devicetree/bindings/usb/
Datmel-usb.txt13 "hclk" for the host clock
25 clock-names = "ohci_clk", "hclk", "uhpck";
63 "hclk" for the AHB clock
74 clock-names = "pclk", "hclk";
91 "hclk" for the host clock
116 clock-names = "hclk", "pclk";
/Linux-v5.10/sound/soc/rockchip/
Drockchip_spdif.c37 struct clk *hclk; member
71 clk_disable_unprepare(spdif->hclk); in rk_spdif_runtime_suspend()
87 ret = clk_prepare_enable(spdif->hclk); in rk_spdif_runtime_resume()
89 dev_err(spdif->dev, "hclk clock enable failed %d\n", ret); in rk_spdif_runtime_resume()
99 clk_disable_unprepare(spdif->hclk); in rk_spdif_runtime_resume()
308 spdif->hclk = devm_clk_get(&pdev->dev, "hclk"); in rk_spdif_probe()
309 if (IS_ERR(spdif->hclk)) in rk_spdif_probe()
310 return PTR_ERR(spdif->hclk); in rk_spdif_probe()
321 spdif->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "hclk", regs, in rk_spdif_probe()
/Linux-v5.10/arch/arm/mach-mv78xx0/
Dcommon.c50 int hclk; in get_hclk() local
53 * HCLK tick rate is configured by DEV_D[7:5] pins. in get_hclk()
57 hclk = 166666667; in get_hclk()
60 hclk = 200000000; in get_hclk()
63 hclk = 266666667; in get_hclk()
66 hclk = 333333333; in get_hclk()
69 hclk = 400000000; in get_hclk()
72 panic("unknown HCLK PLL setting: %.8x\n", in get_hclk()
76 return hclk; in get_hclk()
79 static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk) in get_pclk_l2clk() argument
[all …]
/Linux-v5.10/arch/arm/boot/dts/
Dste-nomadik-stn8815.dtsi226 /* HCLK divides the PLL1 with 1,2,3 or 4 */
227 hclk: hclk@0 { label
229 compatible = "st,nomadik-hclk-clock";
232 /* The PCLK domain uses HCLK right off */
238 clocks = <&hclk>;
302 clocks = <&hclk>;
308 clocks = <&hclk>;
314 clocks = <&hclk>;
320 clocks = <&hclk>;
326 clocks = <&hclk>;
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/clock/
Dst,nomadik.txt34 HCLK nodes: these represent the clock gates on individual
35 lines from the HCLK clock tree and the gate for individual
38 Requires properties for the HCLK nodes:
39 - compatible: must be "st,nomadik-hclk-clock"
/Linux-v5.10/Documentation/devicetree/bindings/mtd/
Dfsmc-nand.txt19 byte 2 THIZ : number of HCLK clock cycles during which the data bus is
23 byte 3 THOLD : number of HCLK clock cycles to hold the address (and data
26 byte 4 TWAIT : number of HCLK clock cycles to assert the command to the
29 byte 5 TSET : number of HCLK clock cycles to assert the address before the
/Linux-v5.10/drivers/soc/qcom/
Dqcom_gsbi.c111 struct clk *hclk; member
183 gsbi->hclk = devm_clk_get(&pdev->dev, "iface"); in gsbi_probe()
184 if (IS_ERR(gsbi->hclk)) in gsbi_probe()
185 return PTR_ERR(gsbi->hclk); in gsbi_probe()
187 clk_prepare_enable(gsbi->hclk); in gsbi_probe()
218 clk_disable_unprepare(gsbi->hclk); in gsbi_probe()
226 clk_disable_unprepare(gsbi->hclk); in gsbi_remove()
/Linux-v5.10/include/linux/soc/samsung/
Ds3c-cpu-freq.h22 * @hclk_tns: HCLK cycle time in 10ths of nano-seconds.
23 * @hclk: The HCLK frequency in Hz.
37 unsigned long hclk; member
73 * @h_divisor: Divisor from FCLK to HCLK.
/Linux-v5.10/arch/arm/mach-lpc32xx/
Dpm.c23 * The ARM CPU clock (HCLK_PLL), HCLK bus clock, and PCLK bus clocks are
24 * derived from the HCLK PLL. The HCLK and PCLK bus rates are divided from
28 * The ARM CPU clock, HCLK bus clock, and PCLK bus clocks are driven from
59 * HCLK PLL state is restored

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