Lines Matching full:hclk
50 int hclk; in get_hclk() local
53 * HCLK tick rate is configured by DEV_D[7:5] pins. in get_hclk()
57 hclk = 166666667; in get_hclk()
60 hclk = 200000000; in get_hclk()
63 hclk = 266666667; in get_hclk()
66 hclk = 333333333; in get_hclk()
69 hclk = 400000000; in get_hclk()
72 panic("unknown HCLK PLL setting: %.8x\n", in get_hclk()
76 return hclk; in get_hclk()
79 static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk) in get_pclk_l2clk() argument
94 * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK in get_pclk_l2clk()
97 *pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1; in get_pclk_l2clk()
388 int hclk; in mv78xx0_init() local
393 hclk = get_hclk(); in mv78xx0_init()
394 get_pclk_l2clk(hclk, core_index, &pclk, &l2clk); in mv78xx0_init()
400 printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000); in mv78xx0_init()