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/Linux-v6.1/drivers/video/fbdev/via/
Dvia-gpio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Support for viafb GPIO ports.
9 #include <linux/gpio/driver.h>
11 #include <linux/via-core.h>
12 #include <linux/via-gpio.h>
16 * The ports we know about. Note that the port-25 gpios are not
29 .vg_name = "VGPIO0", /* Guess - not in datasheet */
81 * GPIO access functions
86 struct viafb_gpio_cfg *cfg = gpiochip_get_data(chip); in via_gpio_set() local
88 struct viafb_gpio *gpio; in via_gpio_set() local
[all …]
/Linux-v6.1/sound/soc/
Dsoc-ac97.c1 // SPDX-License-Identifier: GPL-2.0+
3 // soc-ac97.c -- ALSA SoC Audio Layer AC97 support
11 // with code, comments and ideas from :-
17 #include <linux/gpio.h>
18 #include <linux/gpio/driver.h>
57 return gpio_priv->component; in gpio_to_component()
63 return -EINVAL; in snd_soc_ac97_gpio_request()
73 dev_dbg(component->dev, "set gpio %d to output\n", offset); in snd_soc_ac97_gpio_direction_in()
85 dev_dbg(component->dev, "get gpio %d : %d\n", offset, in snd_soc_ac97_gpio_get()
97 gpio_priv->gpios_set &= ~(1 << offset); in snd_soc_ac97_gpio_set()
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/Linux-v6.1/drivers/pinctrl/renesas/
Dsh_pfc.h1 /* SPDX-License-Identifier: GPL-2.0
12 #include <linux/pinctrl/pinconf-generic.h>
122 * - name: Register name (unused, for documentation purposes only)
123 * - r: Physical register address
124 * - r_width: Width of the register (in bits)
125 * - f_width: Width of the fixed-width register fields (in bits)
126 * - ids: For each register field (from left to right, i.e. MSB to LSB),
140 * - name: Register name (unused, for documentation purposes only)
141 * - r: Physical register address
142 * - r_width: Width of the register (in bits)
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/Linux-v6.1/arch/arm/mach-s3c/
Dgpio-samsung.c1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
11 // Samsung - GPIOlib support
16 #include <linux/gpio.h>
31 #include "regs-gpio.h"
32 #include "gpio-samsung.h"
35 #include "gpio-core.h"
36 #include "gpio-cfg.h"
37 #include "gpio-cfg-helpers.h"
38 #include "hardware-s3c24xx.h"
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Dgpio-cfg.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * S3C Platform - GPIO pin configuration
11 /* This file contains the necessary definitions to get the basic gpio
13 * changing the pull-{up,down} configurations.
27 /* forward declaration if gpio-core.h hasn't been included */
31 * struct samsung_gpio_cfg GPIO configuration
33 * @get_pull: Read the current pull configuration for the GPIO
34 * @set_pull: Set the current pull configuration for the GPIO
35 * @set_config: Set the current configuration for the GPIO
36 * @get_config: Read the current configuration for the GPIO
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Ds3c2443.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/gpio.h>
27 #include "gpio-samsung.h"
32 #include "regs-s3c2443-clock.h"
33 #include "rtc-core-s3c24xx.h"
35 #include "gpio-core.h"
36 #include "gpio-cfg.h"
37 #include "gpio-cfg-helpers.h"
40 #include "adc-core.h"
43 #include "fb-core-s3c24xx.h"
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Ds3c2410.c1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright (c) 2003-2005 Simtec Electronics
14 #include <linux/gpio.h>
29 #include "gpio-samsung.h"
34 #include "regs-clock.h"
40 #include "gpio-core.h"
41 #include "gpio-cfg.h"
42 #include "gpio-cfg-helpers.h"
58 void __init s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no) in s3c2410_init_uarts() argument
60 s3c24xx_init_uartdevs("s3c2410-uart", s3c2410_uart_resources, cfg, no); in s3c2410_init_uarts()
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Ds3c2416.c1 // SPDX-License-Identifier: GPL-2.0+
16 #include <linux/gpio.h>
30 #include "gpio-samsung.h"
31 #include <asm/proc-fns.h>
35 #include "regs-s3c2443-clock.h"
36 #include "rtc-core-s3c24xx.h"
38 #include "gpio-core.h"
39 #include "gpio-cfg.h"
40 #include "gpio-cfg-helpers.h"
46 #include "iic-core.h"
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/Linux-v6.1/Documentation/devicetree/bindings/sound/
Dwm8960.txt7 - compatible : "wlf,wm8960"
9 - reg : the I2C address of the device.
12 - wlf,shared-lrclk: This is a boolean property. If present, the LRCM bit of
18 DACLRC pin. If shared-lrclk is present, no need to enable DAC for captrue.
20 - wlf,capless: This is a boolean property. If present, OUT3 pin will be
24 - wlf,hp-cfg: A list of headphone jack detect configuration register values.
26 hp-cfg[0]: HPSEL[1:0] of R48 (Additional Control 4).
27 hp-cfg[1]: {HPSWEN:HPSWPOL} of R24 (Additional Control 2).
28 hp-cfg[2]: {TOCLKSEL:TOEN} of R23 (Additional Control 1).
30 - wlf,gpio-cfg: A list of GPIO configuration register values.
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Dwlf,wm8903.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
30 - patches@opensource.cirrus.com
39 gpio-controller: true
40 '#gpio-cells':
46 micdet-cfg:
51 micdet-delay:
56 gpio-cfg:
57 $ref: /schemas/types.yaml#/definitions/uint32-array
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Dcs42l56.txt5 - compatible : "cirrus,cs42l56"
7 - reg : the I2C address of the device for I2C
9 - VA-supply, VCP-supply, VLDO-supply : power supplies for the device,
14 - cirrus,gpio-nreset : GPIO controller's phandle and the number
15 of the GPIO used to reset the codec.
17 - cirrus,chgfreq-divisor : Values used to set the Charge Pump Frequency.
24 - cirrus,ain1a-ref-cfg, ain1b-ref-cfg : boolean, If present, AIN1A or AIN1B are configured
25 as a pseudo-differential input referenced to AIN1REF/AIN3A.
27 - cirrus,ain2a-ref-cfg, ain2b-ref-cfg : boolean, If present, AIN2A or AIN2B are configured
28 as a pseudo-differential input referenced to AIN2REF/AIN3B.
[all …]
Dcs42l52.txt5 - compatible : "cirrus,cs42l52"
7 - reg : the I2C address of the device for I2C
11 - cirrus,reset-gpio : GPIO controller's phandle and the number
12 of the GPIO used to reset the codec.
14 - cirrus,chgfreq-divisor : Values used to set the Charge Pump Frequency.
21 - cirrus,mica-differential-cfg : boolean, If present, then the MICA input is configured
23 Single-ended input. Single-ended mode allows for MIC1 or MIC2 muxing for input.
25 - cirrus,micb-differential-cfg : boolean, If present, then the MICB input is configured
27 Single-ended input. Single-ended mode allows for MIC1 or MIC2 muxing for input.
29 - cirrus,micbias-lvl: Set the output voltage level on the MICBIAS Pin
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/Linux-v6.1/drivers/gpio/
Dgpio-sta2x11.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * STMicroelectronics ConneXt (STA2X11) GPIO driver
6 * Based on gpio-ml-ioh.c, Copyright 2010 OKI Semiconductors Ltd.
13 #include <linux/gpio/driver.h>
19 #include <linux/mfd/sta2x11-mfd.h>
43 struct gpio_chip gpio; member
50 * gpio methods
53 static void gsta_gpio_set(struct gpio_chip *gpio, unsigned nr, int val) in gsta_gpio_set() argument
55 struct gsta_gpio *chip = gpiochip_get_data(gpio); in gsta_gpio_set()
56 struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK]; in gsta_gpio_set()
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Dgpio-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/gpio/driver.h>
23 #include <linux/pinctrl/pinconf-generic.h>
27 #include "../pinctrl/pinctrl-rockchip.h"
29 #define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */
30 #define GPIO_TYPE_V2 (0x01000C2B) /* GPIO Version ID 0x01000C2B */
31 #define GPIO_TYPE_V2_1 (0x0101157C) /* GPIO Version ID 0x0101157C */
79 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel()
81 if (bank->gpio_type == GPIO_TYPE_V2) in rockchip_gpio_writel()
90 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_readl()
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/Linux-v6.1/drivers/platform/x86/intel/int3472/
Dclk_and_regulator.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
8 #include <linux/gpio/consumer.h>
25 gpiod_set_value_cansleep(clk->ena_gpio, 1); in skl_int3472_clk_prepare()
26 gpiod_set_value_cansleep(clk->led_gpio, 1); in skl_int3472_clk_prepare()
35 gpiod_set_value_cansleep(clk->ena_gpio, 0); in skl_int3472_clk_unprepare()
36 gpiod_set_value_cansleep(clk->led_gpio, 0); in skl_int3472_clk_unprepare()
42 * We're just turning a GPIO on to enable the clock, which operation in skl_int3472_clk_enable()
44 * .prepare() can, we toggle the GPIO in .prepare() instead. Thus, in skl_int3472_clk_enable()
60 obj = skl_int3472_get_acpi_buffer(int3472->sensor, "SSDB"); in skl_int3472_get_clk_frequency()
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/Linux-v6.1/drivers/regulator/
Dgpio-regulator.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * gpio-regulator.c
14 * Roger Quadros <ext-roger.quadros@nokia.com>
17 * non-controllable regulators, as well as for allowing testing on
28 #include <linux/regulator/gpio-regulator.h>
29 #include <linux/gpio/consumer.h>
50 for (ptr = 0; ptr < data->nr_states; ptr++) in gpio_regulator_get_value()
51 if (data->states[ptr].gpios == data->state) in gpio_regulator_get_value()
52 return data->states[ptr].value; in gpio_regulator_get_value()
54 return -EINVAL; in gpio_regulator_get_value()
[all …]
Dfixed.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * Roger Quadros <ext-roger.quadros@nokia.com>
13 * non-controllable regulators, as well as for allowing testing on
25 #include <linux/gpio/consumer.h>
53 ret = clk_prepare_enable(priv->enable_clock); in reg_clock_enable()
57 priv->enable_counter++; in reg_clock_enable()
66 clk_disable_unprepare(priv->enable_clock); in reg_clock_disable()
67 priv->enable_counter--; in reg_clock_disable()
75 struct device *dev = rdev->dev.parent; in reg_domain_enable()
78 ret = dev_pm_genpd_set_performance_state(dev, priv->performance_state); in reg_domain_enable()
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Dlp8788-buck.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI LP8788 MFD - buck regulator driver
16 #include <linux/gpio.h>
102 struct lp8788_buck1_dvs *dvs = (struct lp8788_buck1_dvs *)buck->dvs; in lp8788_buck1_set_dvs()
108 pinstate = dvs->vsel == DVS_SEL_V0 ? DVS_LOW : DVS_HIGH; in lp8788_buck1_set_dvs()
109 if (gpio_is_valid(dvs->gpio)) in lp8788_buck1_set_dvs()
110 gpio_set_value(dvs->gpio, pinstate); in lp8788_buck1_set_dvs()
115 struct lp8788_buck2_dvs *dvs = (struct lp8788_buck2_dvs *)buck->dvs; in lp8788_buck2_set_dvs()
121 switch (dvs->vsel) { in lp8788_buck2_set_dvs()
142 if (gpio_is_valid(dvs->gpio[0])) in lp8788_buck2_set_dvs()
[all …]
/Linux-v6.1/drivers/hid/
Dhid-cp2112.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * hid-cp2112.c - Silicon Labs HID USB to SMBus master bridge
10 * SMBus controller for talking to slave devices and 8 GPIO pins. The
16 …* https://www.silabs.com/documents/public/application-notes/an495-cp2112-interface-specification…
19 #include <linux/gpio/consumer.h>
20 #include <linux/gpio/machine.h>
21 #include <linux/gpio/driver.h>
28 #include "hid-ids.h"
179 MODULE_PARM_DESC(gpio_push_pull, "GPIO push-pull configuration bitmask");
184 struct hid_device *hdev = dev->hdev; in cp2112_gpio_direction_input()
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/Linux-v6.1/arch/arm/boot/dts/
Dtegra30-pegatron-chagall.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra30-cpu-opp.dtsi"
10 #include "tegra30-cpu-opp-microvolt.dtsi"
11 #include "tegra30-asus-lvds-display.dtsi"
16 chassis-type = "tablet";
35 * pre-existing /chosen node to be available to insert the
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Dtegra30-asus-tf700t.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
20 remote-endpoint = <&bridge_input>;
21 bus-width = <24>;
36 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
44 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
52 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
60 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
68 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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/Linux-v6.1/Documentation/devicetree/bindings/pci/
Dqcom,pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
15 - qcom,sdx55-pcie-ep
16 - qcom,sm8450-pcie-ep
20 - description: Qualcomm-specific PARF configuration registers
21 - description: DesignWare PCIe registers
22 - description: External local bus interface registers
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/Linux-v6.1/arch/arm64/boot/dts/ti/
Dk3-j721s2-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 atf-sram@0 {
20 tifs-sram@1f0000 {
24 l3cache-sram@200000 {
29 gic500: interrupt-controller@1800000 {
30 compatible = "arm,gic-v3";
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/Linux-v6.1/drivers/pinctrl/nuvoton/
Dpinctrl-wpcm450.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2016-2018 Nuvoton Technology corporation.
4 // Copyright (c) 2021-2022 Jonathan Neuschäfer
7 // - Pin mux registers, in the GCR (general control registers) block
8 // - GPIO registers, specific to each GPIO bank
9 // - GPIO event (interrupt) registers, located centrally in the GPIO register
10 // block, shared between all GPIO banks
14 #include <linux/gpio/driver.h>
24 #include <linux/pinctrl/pinconf-generic.h>
35 /* GPIO event (interrupt) registers */
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/Linux-v6.1/drivers/gpu/drm/tiny/
Dst7735r.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/dma-buf.h>
13 #include <linux/gpio/consumer.h>
55 const struct st7735r_cfg *cfg; member
62 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev); in st7735r_pipe_enable()
65 struct mipi_dbi *dbi = &dbidev->dbi; in st7735r_pipe_enable()
69 if (!drm_dev_enter(pipe->crtc.dev, &idx)) in st7735r_pipe_enable()
95 switch (dbidev->rotation) { in st7735r_pipe_enable()
110 if (priv->cfg->rgb) in st7735r_pipe_enable()
170 { .compatible = "jianda,jd-t18003-t01", .data = &jd_t18003_t01_cfg },
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