Lines Matching +full:gpio +full:- +full:cfg
1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
11 // Samsung - GPIOlib support
16 #include <linux/gpio.h>
31 #include "regs-gpio.h"
32 #include "gpio-samsung.h"
35 #include "gpio-core.h"
36 #include "gpio-cfg.h"
37 #include "gpio-cfg-helpers.h"
38 #include "hardware-s3c24xx.h"
44 void __iomem *reg = chip->base + 0x08; in samsung_gpio_setpull_updown()
59 void __iomem *reg = chip->base + 0x08; in samsung_gpio_getpull_updown()
113 void __iomem *reg = chip->base + 0x08; in s3c24xx_gpio_setpull_1()
121 return -EINVAL; in s3c24xx_gpio_setpull_1()
131 void __iomem *reg = chip->base + 0x08; in s3c24xx_gpio_getpull_1()
163 * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration.
164 * @chip: The gpio chip that is being configured.
165 * @off: The offset for the GPIO being configured.
166 * @cfg: The configuration value to set.
168 * This helper deal with the GPIO cases where the control register
169 * has two bits of configuration per gpio, which have the following
177 unsigned int off, unsigned int cfg) in samsung_gpio_setcfg_2bit() argument
179 void __iomem *reg = chip->base; in samsung_gpio_setcfg_2bit()
183 if (samsung_gpio_is_cfg_special(cfg)) { in samsung_gpio_setcfg_2bit()
184 cfg &= 0xf; in samsung_gpio_setcfg_2bit()
185 if (cfg > 3) in samsung_gpio_setcfg_2bit()
186 return -EINVAL; in samsung_gpio_setcfg_2bit()
188 cfg <<= shift; in samsung_gpio_setcfg_2bit()
193 con |= cfg; in samsung_gpio_setcfg_2bit()
200 * samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read.
201 * @chip: The gpio chip that is being configured.
202 * @off: The offset for the GPIO being configured.
214 con = __raw_readl(chip->base); in samsung_gpio_getcfg_2bit()
223 * samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config.
224 * @chip: The gpio chip that is being configured.
225 * @off: The offset for the GPIO being configured.
226 * @cfg: The configuration value to set.
228 * This helper deal with the GPIO cases where the control register has 4 bits
229 * of control per GPIO, generally in the form of:
240 unsigned int off, unsigned int cfg) in samsung_gpio_setcfg_4bit() argument
242 void __iomem *reg = chip->base; in samsung_gpio_setcfg_4bit()
246 if (off < 8 && chip->chip.ngpio > 8) in samsung_gpio_setcfg_4bit()
247 reg -= 4; in samsung_gpio_setcfg_4bit()
249 if (samsung_gpio_is_cfg_special(cfg)) { in samsung_gpio_setcfg_4bit()
250 cfg &= 0xf; in samsung_gpio_setcfg_4bit()
251 cfg <<= shift; in samsung_gpio_setcfg_4bit()
256 con |= cfg; in samsung_gpio_setcfg_4bit()
263 * samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read.
264 * @chip: The gpio chip that is being configured.
265 * @off: The offset for the GPIO being configured.
267 * The reverse of samsung_gpio_setcfg_4bit(), turning a gpio configuration
277 void __iomem *reg = chip->base; in samsung_gpio_getcfg_4bit()
281 if (off < 8 && chip->chip.ngpio > 8) in samsung_gpio_getcfg_4bit()
282 reg -= 4; in samsung_gpio_getcfg_4bit()
294 * s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A)
295 * @chip: The gpio chip that is being configured.
296 * @off: The offset for the GPIO being configured.
297 * @cfg: The configuration value to set.
299 * This helper deal with the GPIO cases where the control register
300 * has one bit of configuration for the gpio, where setting the bit
305 unsigned int off, unsigned int cfg) in s3c24xx_gpio_setcfg_abank() argument
307 void __iomem *reg = chip->base; in s3c24xx_gpio_setcfg_abank()
311 if (samsung_gpio_is_cfg_special(cfg)) { in s3c24xx_gpio_setcfg_abank()
312 cfg &= 0xf; in s3c24xx_gpio_setcfg_abank()
315 cfg -= 1; in s3c24xx_gpio_setcfg_abank()
316 if (cfg > 1) in s3c24xx_gpio_setcfg_abank()
317 return -EINVAL; in s3c24xx_gpio_setcfg_abank()
319 cfg <<= shift; in s3c24xx_gpio_setcfg_abank()
324 con |= cfg; in s3c24xx_gpio_setcfg_abank()
331 * s3c24xx_gpio_getcfg_abank - S3C24XX style GPIO configuration read (Bank A)
332 * @chip: The gpio chip that is being configured.
333 * @off: The offset for the GPIO being configured.
335 * The reverse of s3c24xx_gpio_setcfg_abank() turning an GPIO into a usable
336 * GPIO configuration value.
347 con = __raw_readl(chip->base); in s3c24xx_gpio_getcfg_abank()
359 for (; nr_chips > 0; nr_chips--, chipcfg++) { in samsung_gpiolib_set_cfg()
360 if (!chipcfg->set_config) in samsung_gpiolib_set_cfg()
361 chipcfg->set_config = samsung_gpio_setcfg_4bit; in samsung_gpiolib_set_cfg()
362 if (!chipcfg->get_config) in samsung_gpiolib_set_cfg()
363 chipcfg->get_config = samsung_gpio_getcfg_4bit; in samsung_gpiolib_set_cfg()
364 if (!chipcfg->set_pull) in samsung_gpiolib_set_cfg()
365 chipcfg->set_pull = samsung_gpio_setpull_updown; in samsung_gpiolib_set_cfg()
366 if (!chipcfg->get_pull) in samsung_gpiolib_set_cfg()
367 chipcfg->get_pull = samsung_gpio_getpull_updown; in samsung_gpiolib_set_cfg()
418 * Default routines for controlling GPIO, based on the original S3C24XX
419 * GPIO functions which deal with the case where each gpio bank of the
422 * base + 0x00: Control register, 2 bits per gpio
423 * gpio n: 2 bits starting at (2*n)
424 * 00 = input, 01 = output, others mean special-function
425 * base + 0x04: Data register, 1 bit per gpio
432 void __iomem *base = ourchip->base; in samsung_gpiolib_2bit_input()
451 void __iomem *base = ourchip->base; in samsung_gpiolib_2bit_output()
476 * The samsung_gpiolib_4bit routines are to control the gpio banks where
477 * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
480 * base + 0x00: Control register, 4 bits per gpio
481 * gpio n: 4 bits starting at (4*n)
482 * 0000 = input, 0001 = output, others mean special-function
483 * base + 0x04: Data register, 1 bit per gpio
486 * Note, since the data register is one bit per gpio and is at base + 0x4
495 void __iomem *base = ourchip->base; in samsung_gpiolib_4bit_input()
499 if (ourchip->bitmap_gpio_int & BIT(offset)) in samsung_gpiolib_4bit_input()
514 void __iomem *base = ourchip->base; in samsung_gpiolib_4bit_output()
539 * The next set of routines are for the case where the GPIO configuration
540 * registers are 4 bits per GPIO but there is more than one register (the
546 * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
547 * gpio n: 4 bits starting at (4*n)
548 * 0000 = input, 0001 = output, others mean special-function
549 * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
550 * gpio n: 4 bits starting at (4*n)
551 * 0000 = input, 0001 = output, others mean special-function
552 * base + 0x08: Data register, 1 bit per gpio
557 * the data register at ourchip->base + 0x04.
564 void __iomem *base = ourchip->base; in samsung_gpiolib_4bit2_input()
569 offset -= 8; in samsung_gpiolib_4bit2_input()
571 regcon -= 4; in samsung_gpiolib_4bit2_input()
586 void __iomem *base = ourchip->base; in samsung_gpiolib_4bit2_output()
593 con_offset -= 8; in samsung_gpiolib_4bit2_output()
595 regcon -= 4; in samsung_gpiolib_4bit2_output()
622 return -EINVAL; in s3c24xx_gpiolib_banka_input()
629 void __iomem *base = ourchip->base; in s3c24xx_gpiolib_banka_output()
659 void __iomem *base = ourchip->base; in samsung_gpiolib_set()
679 val = __raw_readl(ourchip->base + 0x04); in samsung_gpiolib_get()
693 * easy gpio to samsung_gpio_chip mapping function. If this is the case, then
706 gpn = chip->chip.base; in s3c_gpiolib_track()
707 for (i = 0; i < chip->chip.ngpio; i++, gpn++) { in s3c_gpiolib_track()
715 * samsung_gpiolib_add() - add the Samsung gpio_chip.
718 * This is a wrapper to gpiochip_add() that takes our specific gpio chip
726 struct gpio_chip *gc = &chip->chip; in samsung_gpiolib_add()
729 BUG_ON(!chip->base); in samsung_gpiolib_add()
730 BUG_ON(!gc->label); in samsung_gpiolib_add()
731 BUG_ON(!gc->ngpio); in samsung_gpiolib_add()
733 spin_lock_init(&chip->lock); in samsung_gpiolib_add()
735 if (!gc->direction_input) in samsung_gpiolib_add()
736 gc->direction_input = samsung_gpiolib_2bit_input; in samsung_gpiolib_add()
737 if (!gc->direction_output) in samsung_gpiolib_add()
738 gc->direction_output = samsung_gpiolib_2bit_output; in samsung_gpiolib_add()
739 if (!gc->set) in samsung_gpiolib_add()
740 gc->set = samsung_gpiolib_set; in samsung_gpiolib_add()
741 if (!gc->get) in samsung_gpiolib_add()
742 gc->get = samsung_gpiolib_get; in samsung_gpiolib_add()
745 if (chip->pm != NULL) { in samsung_gpiolib_add()
746 if (!chip->pm->save || !chip->pm->resume) in samsung_gpiolib_add()
747 pr_err("gpio: %s has missing PM functions\n", in samsung_gpiolib_add()
748 gc->label); in samsung_gpiolib_add()
750 pr_err("gpio: %s has no PM function\n", gc->label); in samsung_gpiolib_add()
763 struct gpio_chip *gc = &chip->chip; in s3c24xx_gpiolib_add_chips()
767 if (chip->chip.base >= S3C_GPIO_END) in s3c24xx_gpiolib_add_chips()
770 if (!chip->config) in s3c24xx_gpiolib_add_chips()
771 chip->config = &s3c24xx_gpiocfg_default; in s3c24xx_gpiolib_add_chips()
772 if (!chip->pm) in s3c24xx_gpiolib_add_chips()
773 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit); in s3c24xx_gpiolib_add_chips()
774 if ((base != NULL) && (chip->base == NULL)) in s3c24xx_gpiolib_add_chips()
775 chip->base = base + ((i) * 0x10); in s3c24xx_gpiolib_add_chips()
777 if (!gc->direction_input) in s3c24xx_gpiolib_add_chips()
778 gc->direction_input = samsung_gpiolib_2bit_input; in s3c24xx_gpiolib_add_chips()
779 if (!gc->direction_output) in s3c24xx_gpiolib_add_chips()
780 gc->direction_output = samsung_gpiolib_2bit_output; in s3c24xx_gpiolib_add_chips()
793 chip->chip.direction_input = samsung_gpiolib_2bit_input; in samsung_gpiolib_add_2bit_chips()
794 chip->chip.direction_output = samsung_gpiolib_2bit_output; in samsung_gpiolib_add_2bit_chips()
796 if (!chip->config) in samsung_gpiolib_add_2bit_chips()
797 chip->config = &samsung_gpio_cfgs[7]; in samsung_gpiolib_add_2bit_chips()
798 if (!chip->pm) in samsung_gpiolib_add_2bit_chips()
799 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit); in samsung_gpiolib_add_2bit_chips()
800 if ((base != NULL) && (chip->base == NULL)) in samsung_gpiolib_add_2bit_chips()
801 chip->base = base + ((i) * offset); in samsung_gpiolib_add_2bit_chips()
808 * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
809 * @chip: The gpio chip that is being configured.
810 * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
812 * This helper deal with the GPIO cases where the control register has 4 bits
813 * of control per GPIO, generally in the form of:
829 chip->chip.direction_input = samsung_gpiolib_4bit_input; in samsung_gpiolib_add_4bit_chips()
830 chip->chip.direction_output = samsung_gpiolib_4bit_output; in samsung_gpiolib_add_4bit_chips()
832 if (!chip->config) in samsung_gpiolib_add_4bit_chips()
833 chip->config = &samsung_gpio_cfgs[2]; in samsung_gpiolib_add_4bit_chips()
834 if (!chip->pm) in samsung_gpiolib_add_4bit_chips()
835 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit); in samsung_gpiolib_add_4bit_chips()
836 if ((base != NULL) && (chip->base == NULL)) in samsung_gpiolib_add_4bit_chips()
837 chip->base = base + ((i) * 0x20); in samsung_gpiolib_add_4bit_chips()
839 chip->bitmap_gpio_int = 0; in samsung_gpiolib_add_4bit_chips()
848 for (; nr_chips > 0; nr_chips--, chip++) { in samsung_gpiolib_add_4bit2_chips()
849 chip->chip.direction_input = samsung_gpiolib_4bit2_input; in samsung_gpiolib_add_4bit2_chips()
850 chip->chip.direction_output = samsung_gpiolib_4bit2_output; in samsung_gpiolib_add_4bit2_chips()
852 if (!chip->config) in samsung_gpiolib_add_4bit2_chips()
853 chip->config = &samsung_gpio_cfgs[2]; in samsung_gpiolib_add_4bit2_chips()
854 if (!chip->pm) in samsung_gpiolib_add_4bit2_chips()
855 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit); in samsung_gpiolib_add_4bit2_chips()
865 return samsung_chip->irq_base + offset; in samsung_gpiolib_to_irq()
879 return IRQ_EINT4 + offset - 4; in s3c24xx_gpiolib_fbank_to_irq()
881 return -EINVAL; in s3c24xx_gpiolib_fbank_to_irq()
888 return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO; in s3c64xx_gpiolib_mbank_to_irq()
893 return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO; in s3c64xx_gpiolib_lbank_to_irq()
1000 * GPIO bank summary:
1171 * Currently there are two drivers that can provide GPIO support for in samsung_gpiolib_init()
1173 * pinctrl-samsung driver is used, providing both GPIO and pin control in samsung_gpiolib_init()
1174 * interfaces. For legacy (non-DT) platforms this driver is used. in samsung_gpiolib_init()
1209 return -EINVAL; in s3c_gpio_cfgpin()
1211 offset = pin - chip->chip.base; in s3c_gpio_cfgpin()
1222 unsigned int cfg) in s3c_gpio_cfgpin_range() argument
1226 for (; nr > 0; nr--, start++) { in s3c_gpio_cfgpin_range()
1227 ret = s3c_gpio_cfgpin(start, cfg); in s3c_gpio_cfgpin_range()
1237 unsigned int cfg, samsung_gpio_pull_t pull) in s3c_gpio_cfgall_range() argument
1241 for (; nr > 0; nr--, start++) { in s3c_gpio_cfgall_range()
1243 ret = s3c_gpio_cfgpin(start, cfg); in s3c_gpio_cfgall_range()
1260 offset = pin - chip->chip.base; in s3c_gpio_getcfg()
1278 return -EINVAL; in s3c_gpio_setpull()
1280 offset = pin - chip->chip.base; in s3c_gpio_setpull()
1298 offset = pin - chip->chip.base; in s3c_gpio_getpull()