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/Linux-v5.10/Documentation/devicetree/bindings/interrupt-controller/
Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
26 - qcom,msm8996-gic-v3
[all …]
/Linux-v5.10/drivers/irqchip/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_IRQCHIP) += irqchip.o
4 obj-$(CONFIG_AL_FIC) += irq-al-fic.o
5 obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o
6 obj-$(CONFIG_ATH79) += irq-ath79-cpu.o
7 obj-$(CONFIG_ATH79) += irq-ath79-misc.o
8 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
9 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
10 obj-$(CONFIG_ARCH_ACTIONS) += irq-owl-sirq.o
11 obj-$(CONFIG_DAVINCI_AINTC) += irq-davinci-aintc.o
[all …]
Dirq-gic-v3-its-fsl-mc-msi.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
21 .name = "ITS-fMSI",
35 out_id = of_node ? of_msi_map_id(&mc_dev->dev, of_node, mc_dev->icid) : in fsl_mc_msi_domain_get_msi_id()
36 iort_msi_map_id(&mc_dev->dev, mc_dev->icid); in fsl_mc_msi_domain_get_msi_id()
49 return -EINVAL; in its_fsl_mc_msi_prepare()
52 if (!(mc_bus_dev->flags & FSL_MC_IS_DPRC)) in its_fsl_mc_msi_prepare()
53 return -EINVAL; in its_fsl_mc_msi_prepare()
56 * Set the device Id to be passed to the GIC-ITS: in its_fsl_mc_msi_prepare()
61 info->scratchpad[0].ul = fsl_mc_msi_domain_get_msi_id(msi_domain, in its_fsl_mc_msi_prepare()
[all …]
Dirq-gic-v3-its-platform-msi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2015 ARM Limited, All Rights Reserved.
14 .name = "ITS-pMSI",
22 /* Suck the DeviceID out of the msi-parent property */ in of_pmsi_get_dev_id()
26 ret = of_parse_phandle_with_args(dev->of_node, in of_pmsi_get_dev_id()
27 "msi-parent", "#msi-cells", in of_pmsi_get_dev_id()
31 return -EINVAL; in of_pmsi_get_dev_id()
43 return -1; in iort_pmsi_get_dev_id()
53 msi_info = msi_get_domain_info(domain->parent); in its_pmsi_prepare()
55 if (dev->of_node) in its_pmsi_prepare()
[all …]
Dirq-gic-v3-its-pci-msi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2015 ARM Limited, All Rights Reserved.
27 .name = "ITS-MSI",
62 return -EINVAL; in its_pci_msi_prepare()
64 msi_info = msi_get_domain_info(domain->parent); in its_pci_msi_prepare()
72 if (alias_dev != pdev && alias_dev->subordinate) in its_pci_msi_prepare()
73 pci_walk_bus(alias_dev->subordinate, its_pci_msi_vec_count, in its_pci_msi_prepare()
76 /* ITS specific DeviceID, as the core ITS ignores dev. */ in its_pci_msi_prepare()
77 info->scratchpad[0].ul = pci_msi_domain_get_msi_rid(domain, pdev); in its_pci_msi_prepare()
87 if (!info->scratchpad[0].ul) in its_pci_msi_prepare()
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/misc/
Dfsl,qoriq-mc.txt3 The Freescale Management Complex (fsl-mc) is a hardware resource
5 network-oriented packet processing applications. After the fsl-mc
12 For an overview of the DPAA2 architecture and fsl-mc bus see:
16 same hardware "isolation context" and a 10-bit value called an ICID
21 between ICIDs and IOMMUs, so an iommu-map property is used to define
28 For arm-smmu binding, see:
32 The msi-map property is used to associate the devices with both the ITS
36 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
38 For GICv3 and GIC ITS bindings, see:
39 Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml.
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/Linux-v5.10/arch/arm64/boot/dts/arm/
Dfoundation-v8-gicv3.dtsi8 gic: interrupt-controller@2f000000 { label
9 compatible = "arm,gic-v3";
10 #interrupt-cells = <3>;
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-controller;
22 its: msi-controller@2f020000 { label
23 compatible = "arm,gic-v3-its";
24 msi-controller;
25 #msi-cells = <1>;
Dfvp-base-revc.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
18 #include "rtsm_ve-motherboard-rs2.dtsi"
22 compatible = "arm,fvp-base-revc", "arm,vexpress";
23 interrupt-parent = <&gic>;
24 #address-cells = <2>;
25 #size-cells = <2>;
[all …]
/Linux-v5.10/arch/arm64/boot/dts/cavium/
Dthunder2-99xx.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (c) 2013-2016 Broadcom
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc";
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
21 #address-cells = <0x2>;
22 #size-cells = <0x0>;
28 enable-method = "psci";
[all …]
Dthunder-88xx.dtsi2 * Cavium Thunder DTS file - Thunder SoC description
6 * This file is dual-licensed: you can use it either under the terms
24 * MA 02110-1301 USA
51 compatible = "cavium,thunder-88xx";
52 interrupt-parent = <&gic0>;
53 #address-cells = <2>;
54 #size-cells = <2>;
57 compatible = "arm,psci-0.2";
62 #address-cells = <2>;
63 #size-cells = <0>;
[all …]
/Linux-v5.10/arch/arm64/boot/dts/hisilicon/
Dhip05.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip05-d02";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
/Linux-v5.10/arch/arm64/boot/dts/marvell/
Darmada-ap810-ap0.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 /dts-v1/;
14 compatible = "marvell,armada-ap810";
15 #address-cells = <2>;
16 #size-cells = <2>;
24 compatible = "arm,psci-0.2";
28 ap810-ap0 {
29 #address-cells = <2>;
30 #size-cells = <2>;
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/iommu/
Darm,smmu-v3.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
15 revisions, replacing the MMIO register interface with in-memory command
21 pattern: "^iommu@[0-9a-f]*"
23 const: arm,smmu-v3
32 interrupt-names:
[all …]
/Linux-v5.10/arch/arm64/boot/dts/amazon/
Dalpine-v3.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2020, Amazon.com, Inc. or its affiliates. All Rights Reserved
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 model = "Amazon's Annapurna Labs Alpine v3";
12 compatible = "amazon,al-alpine-v3";
14 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
[all …]
Dalpine-v2.dtsi2 * Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 * Antoine Tenart <antoine.tenart@free-electrons.com>
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
35 /dts-v1/;
37 #include <dt-bindings/interrupt-controller/arm-gic.h>
41 compatible = "al,alpine-v2";
42 #address-cells = <2>;
43 #size-cells = <2>;
46 #address-cells = <2>;
[all …]
/Linux-v5.10/include/kvm/
Darm_vgic.h1 /* SPDX-License-Identifier: GPL-2.0-only */
18 #include <linux/irqchip/arm-gic-v4.h>
26 #define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1)
30 #define KVM_IRQCHIP_NUM_PINS (1020 - 32)
41 /* same for all guests, as depending only on the _host's_ GIC model */
43 /* type of the host GIC */
75 /* GIC system register CPU interface */
85 #define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr)
105 * affinity reg (v3).
130 * Callback function pointer to in-kernel devices that can tell us the
[all …]
/Linux-v5.10/Documentation/virt/kvm/devices/
Darm-vgic.rst1 .. SPDX-License-Identifier: GPL-2.0
9 - KVM_DEV_TYPE_ARM_VGIC_V2 ARM Generic Interrupt Controller v2.0
13 controller, requiring emulated user-space devices to inject interrupts to the
18 device and guest ITS devices, see arm-vgic-v3.txt. It is not possible to
26 KVM_VGIC_V2_ADDR_TYPE_DIST (rw, 64-bit)
27 Base address in the guest physical address space of the GIC distributor
31 KVM_VGIC_V2_ADDR_TYPE_CPU (rw, 64-bit)
32 Base address in the guest physical address space of the GIC virtual cpu
39 -E2BIG Address outside of addressable IPA range
40 -EINVAL Incorrectly aligned address
[all …]
/Linux-v5.10/arch/arm64/boot/dts/freescale/
Dfsl-ls1088a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
5 * Copyright 2017-2020 NXP
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
25 #address-cells = <1>;
26 #size-cells = <0>;
[all …]
Dfsl-ls208xa.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
31 #address-cells = <1>;
32 #size-cells = <0>;
38 /* DRAM space - 1, size : 2 GB DRAM */
[all …]
Dfsl-ls1028a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
25 #address-cells = <1>;
26 #size-cells = <0>;
[all …]
Dfsl-lx2160a.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
24 #address-cells = <1>;
[all …]
/Linux-v5.10/arch/arm64/boot/dts/broadcom/stingray/
Dstingray.dtsi4 * Copyright(c) 2015-2017 Broadcom. All rights reserved.
16 * * Neither the name of Broadcom nor the names of its
33 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 interrupt-parent = <&gic>;
38 #address-cells = <2>;
39 #size-cells = <2>;
42 #address-cells = <2>;
43 #size-cells = <0>;
47 compatible = "arm,cortex-a72";
49 enable-method = "psci";
[all …]
/Linux-v5.10/arch/arm64/boot/dts/microchip/
Dsparx5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/microchip,sparx5.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <1>;
23 stdout-path = "serial0:115200n8";
27 #address-cells = <2>;
[all …]
/Linux-v5.10/arch/arm64/kvm/vgic/
Dvgic.h1 /* SPDX-License-Identifier: GPL-2.0-only */
8 #include <linux/irqchip/arm-gic-common.h>
13 #define VGIC_ADDR_UNDEF (-1)
45 * As per Documentation/virt/kvm/devices/arm-vgic-v3.rst,
66 * As per Documentation/virt/kvm/devices/arm-vgic-its.rst,
67 * below macros are defined for ITS table entry encoding.
104 if (irq->config == VGIC_CONFIG_EDGE) in irq_is_pending()
105 return irq->pending_latch; in irq_is_pending()
107 return irq->pending_latch || irq->line_level; in irq_is_pending()
112 return irq->config == VGIC_CONFIG_LEVEL && irq->hw; in vgic_irq_is_mapped_level()
[all …]

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