Lines Matching +full:gic +full:- +full:v3 +full:- +full:its
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
24 #address-cells = <1>;
25 #size-cells = <0>;
27 // 8 clusters having 2 Cortex-A72 cores each
30 compatible = "arm,cortex-a72";
31 enable-method = "psci";
34 d-cache-size = <0x8000>;
35 d-cache-line-size = <64>;
36 d-cache-sets = <128>;
37 i-cache-size = <0xC000>;
38 i-cache-line-size = <64>;
39 i-cache-sets = <192>;
40 next-level-cache = <&cluster0_l2>;
41 cpu-idle-states = <&cpu_pw15>;
42 #cooling-cells = <2>;
47 compatible = "arm,cortex-a72";
48 enable-method = "psci";
51 d-cache-size = <0x8000>;
52 d-cache-line-size = <64>;
53 d-cache-sets = <128>;
54 i-cache-size = <0xC000>;
55 i-cache-line-size = <64>;
56 i-cache-sets = <192>;
57 next-level-cache = <&cluster0_l2>;
58 cpu-idle-states = <&cpu_pw15>;
59 #cooling-cells = <2>;
64 compatible = "arm,cortex-a72";
65 enable-method = "psci";
68 d-cache-size = <0x8000>;
69 d-cache-line-size = <64>;
70 d-cache-sets = <128>;
71 i-cache-size = <0xC000>;
72 i-cache-line-size = <64>;
73 i-cache-sets = <192>;
74 next-level-cache = <&cluster1_l2>;
75 cpu-idle-states = <&cpu_pw15>;
76 #cooling-cells = <2>;
81 compatible = "arm,cortex-a72";
82 enable-method = "psci";
85 d-cache-size = <0x8000>;
86 d-cache-line-size = <64>;
87 d-cache-sets = <128>;
88 i-cache-size = <0xC000>;
89 i-cache-line-size = <64>;
90 i-cache-sets = <192>;
91 next-level-cache = <&cluster1_l2>;
92 cpu-idle-states = <&cpu_pw15>;
93 #cooling-cells = <2>;
98 compatible = "arm,cortex-a72";
99 enable-method = "psci";
102 d-cache-size = <0x8000>;
103 d-cache-line-size = <64>;
104 d-cache-sets = <128>;
105 i-cache-size = <0xC000>;
106 i-cache-line-size = <64>;
107 i-cache-sets = <192>;
108 next-level-cache = <&cluster2_l2>;
109 cpu-idle-states = <&cpu_pw15>;
110 #cooling-cells = <2>;
115 compatible = "arm,cortex-a72";
116 enable-method = "psci";
119 d-cache-size = <0x8000>;
120 d-cache-line-size = <64>;
121 d-cache-sets = <128>;
122 i-cache-size = <0xC000>;
123 i-cache-line-size = <64>;
124 i-cache-sets = <192>;
125 next-level-cache = <&cluster2_l2>;
126 cpu-idle-states = <&cpu_pw15>;
127 #cooling-cells = <2>;
132 compatible = "arm,cortex-a72";
133 enable-method = "psci";
136 d-cache-size = <0x8000>;
137 d-cache-line-size = <64>;
138 d-cache-sets = <128>;
139 i-cache-size = <0xC000>;
140 i-cache-line-size = <64>;
141 i-cache-sets = <192>;
142 next-level-cache = <&cluster3_l2>;
143 cpu-idle-states = <&cpu_pw15>;
144 #cooling-cells = <2>;
149 compatible = "arm,cortex-a72";
150 enable-method = "psci";
153 d-cache-size = <0x8000>;
154 d-cache-line-size = <64>;
155 d-cache-sets = <128>;
156 i-cache-size = <0xC000>;
157 i-cache-line-size = <64>;
158 i-cache-sets = <192>;
159 next-level-cache = <&cluster3_l2>;
160 cpu-idle-states = <&cpu_pw15>;
161 #cooling-cells = <2>;
166 compatible = "arm,cortex-a72";
167 enable-method = "psci";
170 d-cache-size = <0x8000>;
171 d-cache-line-size = <64>;
172 d-cache-sets = <128>;
173 i-cache-size = <0xC000>;
174 i-cache-line-size = <64>;
175 i-cache-sets = <192>;
176 next-level-cache = <&cluster4_l2>;
177 cpu-idle-states = <&cpu_pw15>;
178 #cooling-cells = <2>;
183 compatible = "arm,cortex-a72";
184 enable-method = "psci";
187 d-cache-size = <0x8000>;
188 d-cache-line-size = <64>;
189 d-cache-sets = <128>;
190 i-cache-size = <0xC000>;
191 i-cache-line-size = <64>;
192 i-cache-sets = <192>;
193 next-level-cache = <&cluster4_l2>;
194 cpu-idle-states = <&cpu_pw15>;
195 #cooling-cells = <2>;
200 compatible = "arm,cortex-a72";
201 enable-method = "psci";
204 d-cache-size = <0x8000>;
205 d-cache-line-size = <64>;
206 d-cache-sets = <128>;
207 i-cache-size = <0xC000>;
208 i-cache-line-size = <64>;
209 i-cache-sets = <192>;
210 next-level-cache = <&cluster5_l2>;
211 cpu-idle-states = <&cpu_pw15>;
212 #cooling-cells = <2>;
217 compatible = "arm,cortex-a72";
218 enable-method = "psci";
221 d-cache-size = <0x8000>;
222 d-cache-line-size = <64>;
223 d-cache-sets = <128>;
224 i-cache-size = <0xC000>;
225 i-cache-line-size = <64>;
226 i-cache-sets = <192>;
227 next-level-cache = <&cluster5_l2>;
228 cpu-idle-states = <&cpu_pw15>;
229 #cooling-cells = <2>;
234 compatible = "arm,cortex-a72";
235 enable-method = "psci";
238 d-cache-size = <0x8000>;
239 d-cache-line-size = <64>;
240 d-cache-sets = <128>;
241 i-cache-size = <0xC000>;
242 i-cache-line-size = <64>;
243 i-cache-sets = <192>;
244 next-level-cache = <&cluster6_l2>;
245 cpu-idle-states = <&cpu_pw15>;
246 #cooling-cells = <2>;
251 compatible = "arm,cortex-a72";
252 enable-method = "psci";
255 d-cache-size = <0x8000>;
256 d-cache-line-size = <64>;
257 d-cache-sets = <128>;
258 i-cache-size = <0xC000>;
259 i-cache-line-size = <64>;
260 i-cache-sets = <192>;
261 next-level-cache = <&cluster6_l2>;
262 cpu-idle-states = <&cpu_pw15>;
263 #cooling-cells = <2>;
268 compatible = "arm,cortex-a72";
269 enable-method = "psci";
272 d-cache-size = <0x8000>;
273 d-cache-line-size = <64>;
274 d-cache-sets = <128>;
275 i-cache-size = <0xC000>;
276 i-cache-line-size = <64>;
277 i-cache-sets = <192>;
278 next-level-cache = <&cluster7_l2>;
279 cpu-idle-states = <&cpu_pw15>;
280 #cooling-cells = <2>;
285 compatible = "arm,cortex-a72";
286 enable-method = "psci";
289 d-cache-size = <0x8000>;
290 d-cache-line-size = <64>;
291 d-cache-sets = <128>;
292 i-cache-size = <0xC000>;
293 i-cache-line-size = <64>;
294 i-cache-sets = <192>;
295 next-level-cache = <&cluster7_l2>;
296 cpu-idle-states = <&cpu_pw15>;
297 #cooling-cells = <2>;
300 cluster0_l2: l2-cache0 {
302 cache-size = <0x100000>;
303 cache-line-size = <64>;
304 cache-sets = <1024>;
305 cache-level = <2>;
308 cluster1_l2: l2-cache1 {
310 cache-size = <0x100000>;
311 cache-line-size = <64>;
312 cache-sets = <1024>;
313 cache-level = <2>;
316 cluster2_l2: l2-cache2 {
318 cache-size = <0x100000>;
319 cache-line-size = <64>;
320 cache-sets = <1024>;
321 cache-level = <2>;
324 cluster3_l2: l2-cache3 {
326 cache-size = <0x100000>;
327 cache-line-size = <64>;
328 cache-sets = <1024>;
329 cache-level = <2>;
332 cluster4_l2: l2-cache4 {
334 cache-size = <0x100000>;
335 cache-line-size = <64>;
336 cache-sets = <1024>;
337 cache-level = <2>;
340 cluster5_l2: l2-cache5 {
342 cache-size = <0x100000>;
343 cache-line-size = <64>;
344 cache-sets = <1024>;
345 cache-level = <2>;
348 cluster6_l2: l2-cache6 {
350 cache-size = <0x100000>;
351 cache-line-size = <64>;
352 cache-sets = <1024>;
353 cache-level = <2>;
356 cluster7_l2: l2-cache7 {
358 cache-size = <0x100000>;
359 cache-line-size = <64>;
360 cache-sets = <1024>;
361 cache-level = <2>;
364 cpu_pw15: cpu-pw15 {
365 compatible = "arm,idle-state";
366 idle-state-name = "PW15";
367 arm,psci-suspend-param = <0x0>;
368 entry-latency-us = <2000>;
369 exit-latency-us = <2000>;
370 min-residency-us = <6000>;
374 gic: interrupt-controller@6000000 { label
375 compatible = "arm,gic-v3";
376 reg = <0x0 0x06000000 0 0x10000>, // GIC Dist
382 #interrupt-cells = <3>;
383 #address-cells = <2>;
384 #size-cells = <2>;
386 interrupt-controller;
389 its: gic-its@6020000 { label
390 compatible = "arm,gic-v3-its";
391 msi-controller;
397 compatible = "arm,armv8-timer";
405 compatible = "arm,cortex-a72-pmu";
410 compatible = "arm,psci-0.2";
415 // DRAM space - 1, size : 2 GB DRAM
420 ddr1: memory-controller@1080000 {
421 compatible = "fsl,qoriq-memory-controller";
424 little-endian;
427 ddr2: memory-controller@1090000 {
428 compatible = "fsl,qoriq-memory-controller";
431 little-endian;
434 // One clock unit-sysclk node which bootloader require during DT fix-up
436 compatible = "fixed-clock";
437 #clock-cells = <0>;
438 clock-frequency = <100000000>; // fixed up by bootloader
439 clock-output-names = "sysclk";
442 thermal-zones {
443 cluster6-7 {
444 polling-delay-passive = <1000>;
445 polling-delay = <5000>;
446 thermal-sensors = <&tmu 0>;
449 cluster6_7_alert: cluster6-7-alert {
455 cluster6_7_crit: cluster6-7-crit {
462 cooling-maps {
465 cooling-device =
486 ddr-cluster5 {
487 polling-delay-passive = <1000>;
488 polling-delay = <5000>;
489 thermal-sensors = <&tmu 1>;
492 ddr-cluster5-alert {
498 ddr-cluster5-crit {
507 polling-delay-passive = <1000>;
508 polling-delay = <5000>;
509 thermal-sensors = <&tmu 2>;
512 wriop-alert {
518 wriop-crit {
526 dce-qbman-hsio2 {
527 polling-delay-passive = <1000>;
528 polling-delay = <5000>;
529 thermal-sensors = <&tmu 3>;
532 dce-qbman-alert {
538 dce-qbman-crit {
546 ccn-dpaa-tbu {
547 polling-delay-passive = <1000>;
548 polling-delay = <5000>;
549 thermal-sensors = <&tmu 4>;
552 ccn-dpaa-alert {
558 ccn-dpaa-crit {
566 cluster4-hsio3 {
567 polling-delay-passive = <1000>;
568 polling-delay = <5000>;
569 thermal-sensors = <&tmu 5>;
572 clust4-hsio3-alert {
578 clust4-hsio3-crit {
586 cluster2-3 {
587 polling-delay-passive = <1000>;
588 polling-delay = <5000>;
589 thermal-sensors = <&tmu 6>;
592 cluster2-3-alert {
598 cluster2-3-crit {
608 compatible = "simple-bus";
609 #address-cells = <2>;
610 #size-cells = <2>;
612 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
615 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
616 fsl,sec-era = <10>;
617 #address-cells = <1>;
618 #size-cells = <1>;
622 dma-coherent;
626 compatible = "fsl,sec-v5.0-job-ring",
627 "fsl,sec-v4.0-job-ring";
633 compatible = "fsl,sec-v5.0-job-ring",
634 "fsl,sec-v4.0-job-ring";
640 compatible = "fsl,sec-v5.0-job-ring",
641 "fsl,sec-v4.0-job-ring";
647 compatible = "fsl,sec-v5.0-job-ring",
648 "fsl,sec-v4.0-job-ring";
654 clockgen: clock-controller@1300000 {
655 compatible = "fsl,lx2160a-clockgen";
657 #clock-cells = <2>;
662 compatible = "fsl,lx2160a-dcfg", "syscon";
664 little-endian;
668 compatible = "fsl,qoriq-tmu";
671 fsl,tmu-range = <0x800000e6 0x8001017d>;
672 fsl,tmu-calibration =
677 little-endian;
678 #thermal-sensor-cells = <1>;
682 compatible = "fsl,vf610-i2c";
683 #address-cells = <1>;
684 #size-cells = <0>;
687 clock-names = "i2c";
689 scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
694 compatible = "fsl,vf610-i2c";
695 #address-cells = <1>;
696 #size-cells = <0>;
699 clock-names = "i2c";
705 compatible = "fsl,vf610-i2c";
706 #address-cells = <1>;
707 #size-cells = <0>;
710 clock-names = "i2c";
716 compatible = "fsl,vf610-i2c";
717 #address-cells = <1>;
718 #size-cells = <0>;
721 clock-names = "i2c";
727 compatible = "fsl,vf610-i2c";
728 #address-cells = <1>;
729 #size-cells = <0>;
732 clock-names = "i2c";
734 scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>;
739 compatible = "fsl,vf610-i2c";
740 #address-cells = <1>;
741 #size-cells = <0>;
744 clock-names = "i2c";
750 compatible = "fsl,vf610-i2c";
751 #address-cells = <1>;
752 #size-cells = <0>;
755 clock-names = "i2c";
761 compatible = "fsl,vf610-i2c";
762 #address-cells = <1>;
763 #size-cells = <0>;
766 clock-names = "i2c";
772 compatible = "nxp,lx2160a-fspi";
773 #address-cells = <1>;
774 #size-cells = <0>;
777 reg-names = "fspi_base", "fspi_mmap";
780 clock-names = "fspi_en", "fspi";
785 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
786 #address-cells = <1>;
787 #size-cells = <0>;
791 clock-names = "dspi";
792 spi-num-chipselects = <5>;
793 bus-num = <0>;
798 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
799 #address-cells = <1>;
800 #size-cells = <0>;
804 clock-names = "dspi";
805 spi-num-chipselects = <5>;
806 bus-num = <1>;
811 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
812 #address-cells = <1>;
813 #size-cells = <0>;
817 clock-names = "dspi";
818 spi-num-chipselects = <5>;
819 bus-num = <2>;
828 dma-coherent;
829 voltage-ranges = <1800 1800 3300 3300>;
830 sdhci,auto-cmd12;
831 little-endian;
832 bus-width = <4>;
841 dma-coherent;
842 voltage-ranges = <1800 1800 3300 3300>;
843 sdhci,auto-cmd12;
844 broken-cd;
845 little-endian;
846 bus-width = <4>;
851 compatible = "arm,sbsa-uart","arm,pl011";
854 current-speed = <115200>;
859 compatible = "arm,sbsa-uart","arm,pl011";
862 current-speed = <115200>;
867 compatible = "arm,sbsa-uart","arm,pl011";
870 current-speed = <115200>;
875 compatible = "arm,sbsa-uart","arm,pl011";
878 current-speed = <115200>;
883 compatible = "fsl,qoriq-gpio";
886 gpio-controller;
887 little-endian;
888 #gpio-cells = <2>;
889 interrupt-controller;
890 #interrupt-cells = <2>;
894 compatible = "fsl,qoriq-gpio";
897 gpio-controller;
898 little-endian;
899 #gpio-cells = <2>;
900 interrupt-controller;
901 #interrupt-cells = <2>;
905 compatible = "fsl,qoriq-gpio";
908 gpio-controller;
909 little-endian;
910 #gpio-cells = <2>;
911 interrupt-controller;
912 #interrupt-cells = <2>;
916 compatible = "fsl,qoriq-gpio";
919 gpio-controller;
920 little-endian;
921 #gpio-cells = <2>;
922 interrupt-controller;
923 #interrupt-cells = <2>;
927 compatible = "arm,sbsa-gwdt";
931 timeout-sec = <30>;
934 rcpm: power-controller@1e34040 {
935 compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+";
937 #fsl,rcpm-wakeup-cells = <7>;
938 little-endian;
942 compatible = "fsl,lx2160a-ftm-alarm";
944 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
953 snps,quirk-frame-length-adjustment = <0x20>;
955 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
964 snps,quirk-frame-length-adjustment = <0x20>;
966 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
971 compatible = "fsl,lx2160a-ahci";
974 reg-names = "ahci", "sata-ecc";
977 dma-coherent;
982 compatible = "fsl,lx2160a-ahci";
985 reg-names = "ahci", "sata-ecc";
988 dma-coherent;
993 compatible = "fsl,lx2160a-ahci";
996 reg-names = "ahci", "sata-ecc";
999 dma-coherent;
1004 compatible = "fsl,lx2160a-ahci";
1007 reg-names = "ahci", "sata-ecc";
1010 dma-coherent;
1015 compatible = "fsl,lx2160a-pcie";
1018 reg-names = "csr_axi_slave", "config_axi_slave";
1022 interrupt-names = "aer", "pme", "intr";
1023 #address-cells = <3>;
1024 #size-cells = <2>;
1026 dma-coherent;
1027 apio-wins = <8>;
1028 ppio-wins = <8>;
1029 bus-range = <0x0 0xff>;
1030 … ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1031 msi-parent = <&its>;
1032 #interrupt-cells = <1>;
1033 interrupt-map-mask = <0 0 0 7>;
1034 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1035 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1036 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1037 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1038 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1043 compatible = "fsl,lx2160a-pcie";
1046 reg-names = "csr_axi_slave", "config_axi_slave";
1050 interrupt-names = "aer", "pme", "intr";
1051 #address-cells = <3>;
1052 #size-cells = <2>;
1054 dma-coherent;
1055 apio-wins = <8>;
1056 ppio-wins = <8>;
1057 bus-range = <0x0 0xff>;
1058 … ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1059 msi-parent = <&its>;
1060 #interrupt-cells = <1>;
1061 interrupt-map-mask = <0 0 0 7>;
1062 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1063 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1064 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1065 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1066 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1071 compatible = "fsl,lx2160a-pcie";
1074 reg-names = "csr_axi_slave", "config_axi_slave";
1078 interrupt-names = "aer", "pme", "intr";
1079 #address-cells = <3>;
1080 #size-cells = <2>;
1082 dma-coherent;
1083 apio-wins = <256>;
1084 ppio-wins = <24>;
1085 bus-range = <0x0 0xff>;
1086 … ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1087 msi-parent = <&its>;
1088 #interrupt-cells = <1>;
1089 interrupt-map-mask = <0 0 0 7>;
1090 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1091 <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1092 <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1093 <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1094 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1099 compatible = "fsl,lx2160a-pcie";
1102 reg-names = "csr_axi_slave", "config_axi_slave";
1106 interrupt-names = "aer", "pme", "intr";
1107 #address-cells = <3>;
1108 #size-cells = <2>;
1110 dma-coherent;
1111 apio-wins = <8>;
1112 ppio-wins = <8>;
1113 bus-range = <0x0 0xff>;
1114 … ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1115 msi-parent = <&its>;
1116 #interrupt-cells = <1>;
1117 interrupt-map-mask = <0 0 0 7>;
1118 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1119 <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1120 <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1121 <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1122 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1127 compatible = "fsl,lx2160a-pcie";
1130 reg-names = "csr_axi_slave", "config_axi_slave";
1134 interrupt-names = "aer", "pme", "intr";
1135 #address-cells = <3>;
1136 #size-cells = <2>;
1138 dma-coherent;
1139 apio-wins = <256>;
1140 ppio-wins = <24>;
1141 bus-range = <0x0 0xff>;
1142 … ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1143 msi-parent = <&its>;
1144 #interrupt-cells = <1>;
1145 interrupt-map-mask = <0 0 0 7>;
1146 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
1147 <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1148 <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1149 <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
1150 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1155 compatible = "fsl,lx2160a-pcie";
1158 reg-names = "csr_axi_slave", "config_axi_slave";
1162 interrupt-names = "aer", "pme", "intr";
1163 #address-cells = <3>;
1164 #size-cells = <2>;
1166 dma-coherent;
1167 apio-wins = <8>;
1168 ppio-wins = <8>;
1169 bus-range = <0x0 0xff>;
1170 … ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1171 msi-parent = <&its>;
1172 #interrupt-cells = <1>;
1173 interrupt-map-mask = <0 0 0 7>;
1174 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1175 <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1176 <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1177 <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1178 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1183 compatible = "arm,mmu-500";
1185 #iommu-cells = <1>;
1186 #global-interrupts = <14>;
1191 // global non-secure fault
1193 // combined non-secure
1195 // performance counter interrupts 0-9
1271 dma-coherent;
1275 compatible = "fsl,dpaa2-console";
1279 ptp-timer@8b95000 {
1280 compatible = "fsl,dpaa2-ptp";
1283 little-endian;
1284 fsl,extts-fifo;
1287 /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
1289 compatible = "fsl,fman-memac-mdio";
1292 #address-cells = <1>;
1293 #size-cells = <0>;
1294 little-endian;
1299 compatible = "fsl,fman-memac-mdio";
1302 little-endian;
1303 #address-cells = <1>;
1304 #size-cells = <0>;
1308 fsl_mc: fsl-mc@80c000000 {
1309 compatible = "fsl,qoriq-mc";
1312 msi-parent = <&its>;
1313 /* iommu-map property is fixed up by u-boot */
1314 iommu-map = <0 &smmu 0 0>;
1315 dma-coherent;
1316 #address-cells = <3>;
1317 #size-cells = <1>;
1320 * Region type 0x0 - MC portals
1321 * Region type 0x1 - QBMAN portals
1330 #address-cells = <1>;
1331 #size-cells = <0>;
1334 compatible = "fsl,qoriq-mc-dpmac";
1339 compatible = "fsl,qoriq-mc-dpmac";
1344 compatible = "fsl,qoriq-mc-dpmac";
1349 compatible = "fsl,qoriq-mc-dpmac";
1354 compatible = "fsl,qoriq-mc-dpmac";
1359 compatible = "fsl,qoriq-mc-dpmac";
1364 compatible = "fsl,qoriq-mc-dpmac";
1369 compatible = "fsl,qoriq-mc-dpmac";
1374 compatible = "fsl,qoriq-mc-dpmac";
1379 compatible = "fsl,qoriq-mc-dpmac";
1384 compatible = "fsl,qoriq-mc-dpmac";
1389 compatible = "fsl,qoriq-mc-dpmac";
1394 compatible = "fsl,qoriq-mc-dpmac";
1399 compatible = "fsl,qoriq-mc-dpmac";
1404 compatible = "fsl,qoriq-mc-dpmac";
1409 compatible = "fsl,qoriq-mc-dpmac";
1414 compatible = "fsl,qoriq-mc-dpmac";
1419 compatible = "fsl,qoriq-mc-dpmac";