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/Linux-v5.15/arch/arc/mm/
Ddma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 #include <linux/dma-map-ops.h>
11 * ARCH specific callbacks for generic noncoherent DMA ops
12 * - hardware IOC not available (or "dma-coherent" not set for device in DT)
13 * - But still handle both coherent and non-coherent requests from caller
15 * For DMA coherent hardware (IOC) generic code suffices
23 * Yeah this bit us - STAR 9000898266 in arch_dma_prep_coherent()
37 * dma-mapping: provide a generic dma-noncoherent implementation)"
40 * |----------------------------------------------------------------
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/Linux-v5.15/arch/arc/boot/dts/
Daxc003_idu.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
14 #address-cells = <2>;
15 #size-cells = <2>;
18 compatible = "simple-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
24 input_clk: input-clk {
25 #clock-cells = <0>;
26 compatible = "fixed-clock";
27 clock-frequency = <33333333>;
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Daxc003.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
14 #address-cells = <2>;
15 #size-cells = <2>;
18 compatible = "simple-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
24 input_clk: input-clk {
25 #clock-cells = <0>;
26 compatible = "fixed-clock";
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/Linux-v5.15/kernel/dma/
Dcoherent.c1 // SPDX-License-Identifier: GPL-2.0
3 * Coherent per-device memory handling.
10 #include <linux/dma-direct.h>
11 #include <linux/dma-map-ops.h>
25 if (dev && dev->dma_mem) in dev_get_coherent_memory()
26 return dev->dma_mem; in dev_get_coherent_memory()
33 if (mem->use_dev_dma_pfn_offset) in dma_get_device_base()
34 return phys_to_dma(dev, PFN_PHYS(mem->pfn_base)); in dma_get_device_base()
35 return mem->device_base; in dma_get_device_base()
47 return ERR_PTR(-EINVAL); in dma_init_coherent_memory()
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/Linux-v5.15/arch/arm/mm/
Ddma-mapping-nommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Based on linux/arch/arm/mm/dma-mapping.c
5 * Copyright (C) 2000-2004 Russell King
8 #include <linux/dma-map-ops.h>
14 #include "dma.h"
37 const struct iommu_ops *iommu, bool coherent) in arch_setup_dma_ops() argument
42 * coherent if no cache has been detected. Note that it is not in arch_setup_dma_ops()
46 dev->dma_coherent = cacheid ? coherent : true; in arch_setup_dma_ops()
49 * Assume coherent DMA in case MMU/MPU has not been set up. in arch_setup_dma_ops()
51 dev->dma_coherent = (get_cr() & CR_M) ? coherent : true; in arch_setup_dma_ops()
Ddma-mapping.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mm/dma-mapping.c
5 * Copyright (C) 2000-2004 Russell King
7 * DMA uncached mapping support.
17 #include <linux/dma-direct.h>
18 #include <linux/dma-map-ops.h>
33 #include <asm/dma-iommu.h>
36 #include <xen/swiotlb-xen.h>
38 #include "dma.h"
60 #define COHERENT 1 macro
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/Linux-v5.15/Documentation/devicetree/bindings/dma/xilinx/
Dzynqmp_dma.txt1 Xilinx ZynqMP DMA engine, it does support memory to memory transfers,
3 control and rate control support for slave/peripheral dma access.
6 - compatible : Should be "xlnx,zynqmp-dma-1.0"
7 - reg : Memory map for gdma/adma module access.
8 - interrupts : Should contain DMA channel interrupt.
9 - xlnx,bus-width : Axi buswidth in bits. Should contain 128 or 64
10 - clock-names : List of input clocks "clk_main", "clk_apb"
14 - dma-coherent : Present if dma operations are coherent.
18 fpd_dma_chan1: dma@fd500000 {
19 compatible = "xlnx,zynqmp-dma-1.0";
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/Linux-v5.15/Documentation/devicetree/bindings/dma/
Dapm-xgene-dma.txt1 Applied Micro X-Gene SoC DMA nodes
3 DMA nodes are defined to describe on-chip DMA interfaces in
4 APM X-Gene SoC.
6 Required properties for DMA interfaces:
7 - compatible: Should be "apm,xgene-dma".
8 - device_type: set to "dma".
9 - reg: Address and length of the register set for the device.
11 1st - DMA control and status register address space.
12 2nd - Descriptor ring control and status register address space.
13 3rd - Descriptor ring command register address space.
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Darm-pl330.txt1 * ARM PrimeCell PL330 DMA Controller
3 The ARM PrimeCell PL330 DMA controller can move blocks of memory contents
7 - compatible: should include both "arm,pl330" and "arm,primecell".
8 - reg: physical base address of the controller and length of memory mapped
10 - interrupts: interrupt number to the cpu.
13 - dma-coherent : Present if dma operations are coherent
14 - #dma-cells: must be <1>. used to represent the number of integer
16 - dma-channels: contains the total number of DMA channels supported by the DMAC
17 - dma-requests: contains the total number of DMA requests supported by the DMAC
18 - arm,pl330-broken-no-flushp: quirk for avoiding to execute DMAFLUSHP
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/Linux-v5.15/arch/arm/boot/dts/
Dbcm-nsp.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-nsp.h>
38 #address-cells = <1>;
39 #size-cells = <1>;
42 interrupt-parent = <&gic>;
53 #address-cells = <1>;
54 #size-cells = <0>;
58 compatible = "arm,cortex-a9";
59 next-level-cache = <&L2>;
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/Linux-v5.15/arch/arm64/boot/dts/broadcom/stingray/
Dstingray-usb.dtsi1 // SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause)
6 compatible = "simple-bus";
7 #address-cells = <2>;
8 #size-cells = <2>;
13 * to 40-bit
15 dma-ranges = <0 0 0 0 0x100 0x0>;
17 usbphy0: usb-phy@0 {
18 compatible = "brcm,sr-usb-combo-phy";
20 #phy-cells = <1>;
25 compatible = "generic-xhci";
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/Linux-v5.15/arch/arc/plat-hsdk/
Dplatform.c1 // SPDX-License-Identifier: GPL-2.0-only
36 * --------------------- in hsdk_enable_gpio_intc_wire()
37 * | snps,archs-intc | in hsdk_enable_gpio_intc_wire()
38 * --------------------- in hsdk_enable_gpio_intc_wire()
40 * ---------------------- in hsdk_enable_gpio_intc_wire()
41 * | snps,archs-idu-intc | in hsdk_enable_gpio_intc_wire()
42 * ---------------------- in hsdk_enable_gpio_intc_wire()
46 * ------------------- in hsdk_enable_gpio_intc_wire()
47 * | snps,dw-apb-intc | in hsdk_enable_gpio_intc_wire()
48 * ------------------- in hsdk_enable_gpio_intc_wire()
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/Linux-v5.15/Documentation/devicetree/bindings/crypto/
Dti,sa2ul.yaml1 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tero Kristo <t-kristo@ti.com>
15 - ti,j721e-sa2ul
16 - ti,am654-sa2ul
17 - ti,am64-sa2ul
22 power-domains:
27 - description: TX DMA Channel
28 - description: RX DMA Channel #1
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/Linux-v5.15/drivers/of/
Ddevice.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/dma-direct.h> /* for bus_dma_region */
10 #include <linux/dma-map-ops.h>
21 * of_match_device - Tell if a struct device matches an of_device_id list
31 if ((!matches) || (!dev->of_node)) in of_match_device()
33 return of_match_node(matches, dev->of_node); in of_match_device()
39 BUG_ON(ofdev->dev.of_node == NULL); in of_device_add()
43 ofdev->name = dev_name(&ofdev->dev); in of_device_add()
44 ofdev->id = PLATFORM_DEVID_NONE; in of_device_add()
51 set_dev_node(&ofdev->dev, of_node_to_nid(ofdev->dev.of_node)); in of_device_add()
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/Linux-v5.15/Documentation/driver-api/usb/
Ddma.rst1 USB DMA
5 over how DMA may be used to perform I/O operations. The APIs are detailed
11 The big picture is that USB drivers can continue to ignore most DMA issues,
12 though they still must provide DMA-ready buffers (see
13 Documentation/core-api/dma-api-howto.rst). That's how they've worked through
14 the 2.4 (and earlier) kernels, or they can now be DMA-aware.
16 DMA-aware usb drivers:
18 - New calls enable DMA-aware drivers, letting them allocate dma buffers and
19 manage dma mappings for existing dma-ready buffers (see below).
21 - URBs have an additional "transfer_dma" field, as well as a transfer_flags
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/Linux-v5.15/Documentation/devicetree/bindings/ata/
Dahci-fsl-qoriq.txt4 - reg: Physical base address and size of the controller's register area.
5 - compatible: Compatibility string. Must be 'fsl,<chip>-ahci', where
7 - clocks: Input clock specifier. Refer to common clock bindings.
8 - interrupts: Interrupt specifier. Refer to interrupt binding.
11 - dma-coherent: Enable AHCI coherent DMA operation.
12 - reg-names: register area names when there are more than 1 register area.
16 compatible = "fsl,ls1021a-ahci";
20 dma-coherent;
Dapm-xgene.txt1 * APM X-Gene 6.0 Gb/s SATA host controller nodes
3 SATA host controller nodes are defined to describe on-chip Serial ATA
7 - compatible : Shall contain:
8 * "apm,xgene-ahci"
9 - reg : First memory resource shall be the AHCI memory
19 - interrupts : Interrupt-specifier for SATA host controller IRQ.
20 - clocks : Reference to the clock entry.
21 - phys : A list of phandles + phy-specifiers, one for each
22 entry in phy-names.
23 - phy-names : Should contain:
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/Linux-v5.15/arch/mips/mm/
Ddma-noncoherent.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2000, 2001, 06 Ralf Baechle <ralf@linux-mips.org>
7 #include <linux/dma-direct.h>
8 #include <linux/dma-map-ops.h>
12 #include <asm/cpu-type.h>
18 * flush post-DMA.
20 * Warning on the terminology - Linux calls an uncached area coherent; MIPS
21 * terminology calls memory areas with hardware maintained coherency coherent.
24 * However this function is only called on non-I/O-coherent systems and only the
41 * the post-DMA flush/invalidate. in cpu_needs_post_dma_flush()
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/Linux-v5.15/Documentation/devicetree/bindings/pci/
Dxgene-pci.txt1 * AppliedMicro X-Gene PCIe interface
4 - device_type: set to "pci"
5 - compatible: should contain "apm,xgene-pcie" to identify the core.
6 - reg: A list of physical base address and length for each set of controller
7 registers. Must contain an entry for each entry in the reg-names
9 - reg-names: Must include the following entries:
12 - #address-cells: set to <3>
13 - #size-cells: set to <2>
14 - ranges: ranges for the outbound memory, I/O regions.
15 - dma-ranges: ranges for the inbound memory regions.
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Dti,am65-pci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,am65-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: pci-ep.yaml#
19 - ti,am654-pcie-ep
24 reg-names:
26 - const: app
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/Linux-v5.15/arch/arm64/boot/dts/marvell/
Darmada-ap810-ap0.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 /dts-v1/;
14 compatible = "marvell,armada-ap810";
15 #address-cells = <2>;
16 #size-cells = <2>;
24 compatible = "arm,psci-0.2";
28 ap810-ap0 {
29 #address-cells = <2>;
30 #size-cells = <2>;
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Darmada-cp11x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
9 #include <dt-bindings/thermal/thermal.h>
11 #include "armada-common.dtsi"
27 thermal-zones {
28 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) {
29 polling-delay-passive = <0>; /* Interrupt driven */
30 polling-delay = <0>; /* Interrupt driven */
32 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
42 cooling-maps { };
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/Linux-v5.15/drivers/iommu/
Ddma-iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * A fairly generic DMA-API to IOMMU-API glue layer.
5 * Copyright (C) 2014-2015 ARM Ltd.
7 * based in part on arch/arm/mm/dma-mapping.c:
8 * Copyright (C) 2000-2004 Russell King
13 #include <linux/dma-map-ops.h>
14 #include <linux/dma-iommu.h>
27 #include <linux/dma-direct.h>
74 freelist = freelist->freelist; in iommu_dma_entry_dtor()
81 if (cookie->type == IOMMU_DMA_IOVA_COOKIE) in cookie_msi_granule()
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/Linux-v5.15/arch/arm/include/asm/
Ddma-mapping.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 * arm_dma_alloc - allocate consistent memory for DMA
25 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
27 * @handle: bus-specific DMA address
30 * Allocate some memory for a device for performing DMA. This function
31 * allocates pages, and will return the CPU-viewed address, and sets @handle
32 * to be the device-viewed address.
38 * arm_dma_free - free memory allocated by arm_dma_alloc
39 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
41 * @cpu_addr: CPU-view address returned from dma_alloc_coherent
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/Linux-v5.15/Documentation/devicetree/bindings/display/hisilicon/
Dhisi-ade.txt1 Device-Tree bindings for hisilicon ADE display controller driver
8 - compatible: value should be "hisilicon,hi6220-ade".
9 - reg: physical base address and length of the ADE controller's registers.
10 - hisilicon,noc-syscon: ADE NOC QoS syscon.
11 - resets: The ADE reset controller node.
12 - interrupt: the ldi vblank interrupt number used.
13 - clocks: a list of phandle + clock-specifier pairs, one for each entry
14 in clock-names.
15 - clock-names: should contain:
20 - assigned-clocks: Should contain "clk_ade_core" and "clk_codec_jpeg" clocks'
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