counts (full) in projects: Linux-v5.10 - OpenGrok search results

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/Linux-v5.10/tools/perf/util/
D	counts.c	6 #include "counts.h" 11 struct perf_counts counts = zalloc(sizeof(counts)); in perf_counts__new() local 13 if (counts) { in perf_counts__new() 18 free(counts); in perf_counts__new() 22 counts->values = values; in perf_counts__new() 26 xyarray__delete(counts->values); in perf_counts__new() 27 free(counts); in perf_counts__new() 31 counts->loaded = values; in perf_counts__new() 34 return counts; in perf_counts__new() 37 void perf_counts__delete(struct perf_counts *counts) in perf_counts__delete() argument [all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/broadwell/
D	memory.json	3 …"PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L… 13 …"PublicDescription": "This event counts speculative cache line split store-address (STA) uops disp… 98 …"BriefDescription": "Counts the number of times a class of instructions that may cause a transacti… 108 …"BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that ma… 118 …"BriefDescription": "Counts the number of times an instruction execution caused the transactional … 128 …"BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE tr… 137 …"BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an… 141 …"PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Mem… 147 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 314 "PublicDescription": "Counts randomly selected loads with latency value being above four.", [all …]
D	cache.json	3 …"PublicDescription": "This event counts the number of demand Data Read requests that miss L2 cache… 40 …"PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers th… 59 …"PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructio… 87 …"PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers th… 97 …"PublicDescription": "This event counts the number of demand Data Read requests (including request… 107 …"PublicDescription": "This event counts the total number of RFO (read for ownership) requests to L… 117 "PublicDescription": "This event counts the total number of L2 code requests.", 136 …"PublicDescription": "This event counts the total number of requests from the L2 hardware prefetch… 155 "PublicDescription": "This event counts the number of WB requests that hit L2 cache.", 165 …"PublicDescription": "This event counts core-originated cacheable demand requests that miss the la… [all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/skylake/
D	cache.json	3 …"PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not … 13 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.", 23 "PublicDescription": "Counts L2 cache misses when fetching instructions.", 43 …"PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software pref… 63 …"PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructio… 73 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", 83 "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.", 93 …"PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software pref… 103 …"PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D … 113 …"PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2… [all …]
D	memory.json	77 …"BriefDescription": "Counts the number of times a class of instructions that may cause a transacti… 87 …"BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that ma… 97 …"BriefDescription": "Counts the number of times an instruction execution caused the transactional … 107 …"BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE tr… 111 …"PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside a… 117 …"BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an… 126 …"BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 c… 180 …"PublicDescription": "Counts the number of memory ordering Machine Clears detected. Memory Orderin… 187 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 350 …"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to compl… [all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/knightslanding/
D	pipeline.json	9 "BriefDescription": "Counts the number of branch instructions retired" 18 …"BriefDescription": "Counts the number of branch instructions retired that were conditional jumps." 27 …"BriefDescription": "Counts the number of branch instructions retired that were conditional jumps … 36 "BriefDescription": "Counts the number of near CALL branch instructions retired." 45 "BriefDescription": "Counts the number of near relative CALL branch instructions retired." 54 "BriefDescription": "Counts the number of near indirect CALL branch instructions retired." 63 "BriefDescription": "Counts the number of near RET branch instructions retired." 72 …"BriefDescription": "Counts the number of branch instructions retired that were near indirect CALL… 81 "BriefDescription": "Counts the number of far branch instructions retired." 90 "BriefDescription": "Counts the number of mispredicted branch instructions retired" [all …]
D	memory.json	8 … "BriefDescription": "Counts the number of times the machine clears due to memory ordering hazards" 18 …"BriefDescription": "Counts any Prefetch requests that accounts for data responses from MCDRAM Far… 29 …"BriefDescription": "Counts any Prefetch requests that accounts for data responses from MCDRAM Loc… 40 …"BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Far.", 51 …"BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Local… 62 …"BriefDescription": "Counts any Read request that accounts for data responses from MCDRAM Far or … 73 …"BriefDescription": "Counts any Read request that accounts for data responses from MCDRAM Local.", 84 … "BriefDescription": "Counts any Read request that accounts for data responses from DRAM Far.", 95 … "BriefDescription": "Counts any Read request that accounts for data responses from DRAM Local.", 106 …"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for d… [all …]
D	cache.json	8 …"BriefDescription": "Counts the number of MEC requests from the L2Q that reference a cache line (c… 16 …"BriefDescription": "Counts the number of MEC requests that were not accepted into the L2Q because… 24 "BriefDescription": "Counts the total number of L2 cache references." 32 "BriefDescription": "Counts the number of L2 cache misses" 35 …"PublicDescription": "This event counts the number of core cycles the fetch stalls because of an i… 41 …"BriefDescription": "Counts the number of core cycles the fetch stalls because of an icache miss. … 44 …"PublicDescription": "This event counts the number of load micro-ops retired that miss in L1 Data … 50 "BriefDescription": "Counts the number of load micro-ops retired that miss in L1 D cache" 59 "BriefDescription": "Counts the number of load micro-ops retired that hit in the L2", 69 "BriefDescription": "Counts the number of load micro-ops retired that miss in the L2", [all …]
/Linux-v5.10/drivers/net/ethernet/freescale/dpaa2/
D	dpmac.h	147 * @DPMAC_CNT_ING_FRAME_64: counts 64-bytes frames, good or bad. 148 * @DPMAC_CNT_ING_FRAME_127: counts 65- to 127-bytes frames, good or bad. 149 * @DPMAC_CNT_ING_FRAME_255: counts 128- to 255-bytes frames, good or bad. 150 * @DPMAC_CNT_ING_FRAME_511: counts 256- to 511-bytes frames, good or bad. 151 * @DPMAC_CNT_ING_FRAME_1023: counts 512- to 1023-bytes frames, good or bad. 152 * @DPMAC_CNT_ING_FRAME_1518: counts 1024- to 1518-bytes frames, good or bad. 153 * @DPMAC_CNT_ING_FRAME_1519_MAX: counts 1519-bytes frames and larger 156 * @DPMAC_CNT_ING_FRAG: counts frames which are shorter than 64 bytes received 158 * @DPMAC_CNT_ING_JABBER: counts frames longer than the maximum frame length 160 * @DPMAC_CNT_ING_FRAME_DISCARD: counts dropped frames due to internal errors. [all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/goldmont/
D	cache.json	4 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.", 14 …"PublicDescription": "Counts memory requests originating from the core that reference a cache line… 24 …"PublicDescription": "Counts the number of demand and prefetch transactions that the L2 XQ rejects… 34 …Counts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly… 44 …"PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache … 54 …"PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ICache miss. That … 74 …"PublicDescription": "Counts locked memory uops retired. This includes regular locks and bus lock… 86 …"PublicDescription": "Counts load uops retired where the data requested spans a 64 byte cache line… 98 …"PublicDescription": "Counts store uops retired where the data requested spans a 64 byte cache lin… 110 …"PublicDescription": "Counts memory uops retired where the data requested spans a 64 byte cache li… [all …]
D	pipeline.json	3 …Description": "Counts the number of instructions that retire execution. For instructions that cons… 11 …"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The… 19 …Counts the number of reference cycles that the core is not in a halt state. The core enters the ha… 29 …"PublicDescription": "Counts a load blocked from using a store forward, but did not occur because … 40 …"PublicDescription": "Counts a load blocked from using a store forward because of an address/size … 51 …"PublicDescription": "Counts loads that block because their address modulo 4K matches a pending st… 62 …"PublicDescription": "Counts loads blocked because they are unable to find their physical address … 73 "PublicDescription": "Counts anytime a load that retires is blocked for any reason.", 83 …"PublicDescription": "Counts uops issued by the front end and allocated into the back end of the m… 113 …counts only when back-end is requesting more uops and front-end is not able to provide them. When … [all …]
D	frontend.json	4 …Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that… 10 …ences per ICache line that are available in the ICache (hit). This event counts differently than I… 14 …Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and tha… 20 … per ICache line that are not available in the ICache (miss). This event counts differently than I… 24 …Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line. The ev… 30 …"BriefDescription": "References per ICache line. This event counts differently than Intel processo… 34 …Counts the number of times the Microcode Sequencer (MS) starts a flow of uops from the MSROM. It d… 44 …"PublicDescription": "Counts the number of times the prediction (from the predecode cache) for ins…
/Linux-v5.10/tools/perf/pmu-events/arch/x86/silvermont/
D	pipeline.json	4 …"PublicDescription": "ALL_BRANCHES counts the number of any branch instructions retired. Branch p… 10 "BriefDescription": "Counts the number of branch instructions retired..." 14 …"PublicDescription": "JCC counts the number of conditional branch (JCC) instructions retired. Bran… 20 "BriefDescription": "Counts the number of JCC branch instructions retired" 24 …"PublicDescription": "TAKEN_JCC counts the number of taken conditional branch (JCC) instructions r… 30 "BriefDescription": "Counts the number of taken JCC branch instructions retired" 34 …"PublicDescription": "CALL counts the number of near CALL branch instructions retired. Branch pre… 40 "BriefDescription": "Counts the number of near CALL branch instructions retired" 44 …"PublicDescription": "REL_CALL counts the number of near relative CALL branch instructions retired… 50 "BriefDescription": "Counts the number of near relative CALL branch instructions retired" [all …]
D	cache.json	3 …"PublicDescription": "This event counts the number of demand and prefetch transactions that the L2… 9 … "BriefDescription": "Counts the number of request from the L2 that were not accepted into the XQ" 12 …Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full o… 18 …"BriefDescription": "Counts the number of request that were not accepted into the L2Q because the … 21 …"PublicDescription": "This event counts requests originating from the core that references a cache… 30 …"PublicDescription": "This event counts the total number of L2 cache references and the number of … 39 …"PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ICache miss. That … 49 …"PublicDescription": "This event counts the number of retired loads that were prohibited from rece… 58 …"PublicDescription": "This event counts the cases where a forward was technically possible, but di… 67 …"PublicDescription": "This event counts the number of retire stores that experienced cache line bo… [all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/goldmontplus/
D	cache.json	4 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.", 16 …"PublicDescription": "Counts memory requests originating from the core that reference a cache line… 28 …"PublicDescription": "Counts the number of demand and prefetch transactions that the L2 XQ rejects… 40 …Counts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly… 52 …"PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache … 64 …"PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ICache miss. That … 88 …"PublicDescription": "Counts locked memory uops retired. This includes regular locks and bus lock… 101 …"PublicDescription": "Counts load uops retired where the data requested spans a 64 byte cache line… 114 …"PublicDescription": "Counts store uops retired where the data requested spans a 64 byte cache lin… 127 …"PublicDescription": "Counts memory uops retired where the data requested spans a 64 byte cache li… [all …]
D	pipeline.json	5 …Description": "Counts the number of instructions that retire execution. For instructions that cons… 16 …"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The… 27 …Counts the number of reference cycles that the core is not in a halt state. The core enters the ha… 39 …"PublicDescription": "Counts a load blocked from using a store forward, but did not occur because … 51 …"PublicDescription": "Counts a load blocked from using a store forward because of an address/size … 63 …"PublicDescription": "Counts loads that block because their address modulo 4K matches a pending st… 75 …"PublicDescription": "Counts loads blocked because they are unable to find their physical address … 87 "PublicDescription": "Counts anytime a load that retires is blocked for any reason.", 98 …"PublicDescription": "Counts uops issued by the front end and allocated into the back end of the m… 134 …counts only when back-end is requesting more uops and front-end is not able to provide them. When … [all …]
D	frontend.json	4 …Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that… 12 …ences per ICache line that are available in the ICache (hit). This event counts differently than I… 16 …Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and tha… 24 … per ICache line that are not available in the ICache (miss). This event counts differently than I… 28 …Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line. The ev… 36 …"BriefDescription": "References per ICache line. This event counts differently than Intel processo… 40 …Counts the number of times the Microcode Sequencer (MS) starts a flow of uops from the MSROM. It d… 52 …"PublicDescription": "Counts the number of times the prediction (from the predecode cache) for ins…
/Linux-v5.10/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/
D	cache.json	3 …"PublicDescription": "L1 instruction cache refill. This event counts any instruction fetch which m… 9 …"PublicDescription": "L1 instruction TLB refill. This event counts any refill of the instruction L… 15 …"PublicDescription": "L1 data cache refill. This event counts any load or store operation or page … 21 …"PublicDescription": "L1 data cache access. This event counts any load or store operation or page … 27 …"PublicDescription": "L1 data TLB refill. This event counts any refill of the data L1 TLB from the… 33 … 1 instruction cache access or Level 0 Macro-op cache access. This event counts any instruction fe… 39 …"L1 data cache Write-Back. This event counts any write-back of data from the L1 data cache to L2 o… 45 …"PublicDescription": "L2 data cache access. This event counts any transaction from L1 which looks … 51 …"PublicDescription": "L2 data cache refill. This event counts any cacheable transaction from L1 wh… 57 …"PublicDescription": "L2 data cache write-back. This event counts any write-back of data from the … [all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/tremontx/
D	pipeline.json	5 …ublicDescription": "Counts the number of instructions that retire. For instructions that consist o… 11 "BriefDescription": "Counts the number of instructions retired. (Fixed event)" 15 …"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The… 22 "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)" 26 …"PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. … 33 …"BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed… 37 …"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The… 44 "BriefDescription": "Counts the number of unhalted core clock cycles." 48 …"PublicDescription": "Counts reference cycles (at TSC frequency) when core is not halted. This ev… 56 "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency." [all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/icelake/
D	memory.json	4 "PublicDescription": "Counts the number of times a TSX line had a cache conflict.", 15 …"PublicDescription": "Speculatively counts the number Transactional Synchronization Extensions (TS… 22 …"BriefDescription": "Speculatively counts the number TSX Aborts due to a data capacity limitation … 26 …"PublicDescription": "Counts the number of times a TSX Abort was triggered due to a non-release/co… 37 …"PublicDescription": "Counts the number of times a TSX Abort was triggered due to commit but Lock … 48 …"PublicDescription": "Counts the number of times a TSX Abort was triggered due to release/commit b… 59 …"PublicDescription": "Counts the number of times a TSX Abort was triggered due to attempting an un… 70 "PublicDescription": "Counts the number of times we could not allocate Lock Buffer.", 81 "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.", 88 …"BriefDescription": "Counts the number of times a class of instructions that may cause a transacti… [all …]
D	cache.json	4 …"PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not … 15 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.", 26 "PublicDescription": "Counts L2 cache misses when fetching instructions.", 37 "PublicDescription": "Counts demand requests that miss L2 cache.", 48 …"PublicDescription": "Counts Software prefetch requests that miss the L2 cache. This event account… 59 …"PublicDescription": "Counts the number of demand Data Read requests initiated by load instruction… 70 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", 81 "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.", 92 …"PublicDescription": "Counts Software prefetch requests that hit the L2 cache. This event accounts… 103 …"PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D … [all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/haswellx/
D	memory.json	88 …"BriefDescription": "Counts the number of times a class of instructions that may cause a transacti… 97 …"BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that ma… 106 …"BriefDescription": "Counts the number of times an instruction execution caused the transactional … 115 …"BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE tr… 124 …"BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an… 133 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 136 …"PublicDescription": "This event counts the number of memory ordering machine clears detected. Mem… 407 "BriefDescription": "Counts demand data reads miss in the L3", 412 "PublicDescription": "Counts demand data reads miss in the L3", 420 …"BriefDescription": "Counts demand data reads miss the L3 and the data is returned from local dram… [all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/broadwellx/
D	cache.json	8 …"PublicDescription": "This event counts the number of demand Data Read requests that miss L2 cache… 45 …"PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers th… 64 …"PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructio… 92 …"PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers th… 102 …"PublicDescription": "This event counts the number of demand Data Read requests (including request… 112 …"PublicDescription": "This event counts the total number of RFO (read for ownership) requests to L… 122 "PublicDescription": "This event counts the total number of L2 code requests.", 141 …"PublicDescription": "This event counts the total number of requests from the L2 hardware prefetch… 160 "PublicDescription": "This event counts the number of WB requests that hit L2 cache.", 170 …"PublicDescription": "This event counts core-originated cacheable demand requests that miss the la… [all …]
D	memory.json	8 …"PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L… 18 …"PublicDescription": "This event counts speculative cache line split store-address (STA) uops disp… 95 …"BriefDescription": "Counts the number of times a class of instructions that may cause a transacti… 104 …"BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that ma… 114 …"BriefDescription": "Counts the number of times an instruction execution caused the transactional … 124 …"BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE tr… 134 …"BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an… 143 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 146 …"PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Mem… 322 "PublicDescription": "Counts randomly selected loads with latency value being above four.", [all …]
D	pipeline.json	7 …"This event counts the number of instructions retired from execution. For instructions that consis… 16 …"PublicDescription": "This event counts the number of core cycles while the thread is not in a hal… 34 …"PublicDescription": "This event counts the number of reference cycles when the core is not in a h… 44 …"PublicDescription": "This event counts how many times the load operation got the true Block-on-St… 51 …"BriefDescription": "This event counts the number of times that split load operations are temporar… 63 …"PublicDescription": "This event counts false dependencies in MOB when the partial comparison upon… 95 …"PublicDescription": "This event counts the number of cycles during which Resource Allocation Tabl… 105 …"PublicDescription": "This event counts the number of Uops issued by the Resource Allocation Table… 117 …"PublicDescription": "This event counts cycles during which the Resource Allocation Table (RAT) do… 155 …"PublicDescription": "This event counts the number of the divide operations executed. Uses edge-de… [all …]

12 3 4 5 6 7 8 9 10 >>...46