Lines Matching full:counts
4 …"PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not …
15 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
26 "PublicDescription": "Counts L2 cache misses when fetching instructions.",
37 "PublicDescription": "Counts demand requests that miss L2 cache.",
48 …"PublicDescription": "Counts Software prefetch requests that miss the L2 cache. This event account…
59 …"PublicDescription": "Counts the number of demand Data Read requests initiated by load instruction…
70 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
81 "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
92 …"PublicDescription": "Counts Software prefetch requests that hit the L2 cache. This event accounts…
103 …"PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D …
114 …"PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2…
125 "PublicDescription": "Counts the total number of L2 code requests.",
136 "PublicDescription": "Counts demand requests to L2 cache.",
147 …"PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each…
158 "PublicDescription": "Counts duration of L1D miss outstanding in cycles.",
170 …"PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (…
181 …"PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (…
194 …"PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack o…
205 …"PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and …
212 "BriefDescription": "Counts the number of cache lines replaced in L1 data cache."
216 …"PublicDescription": "Counts the number of offcore outstanding demand rfo Reads transactions in th…
228 …"PublicDescription": "Counts the number of offcore outstanding cacheable Core Data Read transactio…
239 …"PublicDescription": "Counts cycles when offcore outstanding cacheable Core Data Read transactions…
251 …"PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction w…
262 …"PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, …
273 …"PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cache…
284 …"PublicDescription": "Counts memory transactions reached the super queue including requests initia…
296 "PublicDescription": "Counts retired load instructions that true miss the STLB.",
309 "PublicDescription": "Counts retired store instructions that true miss the STLB.",
323 "PublicDescription": "Counts retired load instructions with locked access.",
336 … "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.",
349 … "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.",
363 …"PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch in…
376 …"PublicDescription": "Counts all retired store instructions. This event account for SW prefetch in…
390 …"PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 da…
403 "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.",
416 …"PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 ca…
429 …"PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1…
442 "PublicDescription": "Counts retired load instructions missed L2 cache as data sources.",
455 …"PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3…
468 …"PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1…
481 …"PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cros…
494 …"PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core s…
507 …"PublicDescription": "Counts retired load instructions whose data sources were HitM responses from…
520 …"PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without …
532 …"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover …
543 …"PublicDescription": "Counts the cycles for which the thread is active and the superQ cannot take …