| /Linux-v5.15/drivers/media/platform/qcom/venus/ |
| D | hfi_parser.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include "core.h"
17 static void init_codecs(struct venus_core *core) in init_codecs() argument
19 struct hfi_plat_caps *caps = core->caps, *cap; in init_codecs()
22 for_each_set_bit(bit, &core->dec_codecs, MAX_CODEC_NUM) { in init_codecs()
23 cap = &caps[core->codecs_count++]; in init_codecs()
24 cap->codec = BIT(bit); in init_codecs()
25 cap->domain = VIDC_SESSION_TYPE_DEC; in init_codecs()
26 cap->valid = false; in init_codecs()
29 for_each_set_bit(bit, &core->enc_codecs, MAX_CODEC_NUM) { in init_codecs()
[all …]
|
| /Linux-v5.15/arch/arm/mach-omap2/ |
| D | powerdomains44xx_data.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2009-2011 Texas Instruments, Inc.
6 * Copyright (C) 2009-2011 Nokia Corporation
9 * Benoit Cousson (b-cousson@ti.com)
14 * with the public linux-omap@vger.kernel.org mailing list and the
16 * up-to-date with the file contents.
24 #include "prcm-common.h"
26 #include "prm-regbits-44xx.h"
30 /* core_44xx_pwrdm: CORE power domain */
33 .voltdm = { .name = "core" },
[all …]
|
| D | powerdomains54xx_data.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * Benoit Cousson (b-cousson@ti.com)
13 * with the public linux-omap@vger.kernel.org mailing list and the
15 * up-to-date with the file contents.
23 #include "prcm-common.h"
28 /* core_54xx_pwrdm: CORE power domain */
31 .voltdm = { .name = "core" },
54 /* abe_54xx_pwrdm: Audio back end power domain */
57 .voltdm = { .name = "core" },
74 /* coreaon_54xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
[all …]
|
| /Linux-v5.15/Documentation/devicetree/bindings/arm/tegra/ |
| D | nvidia,tegra20-pmc.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra20-pmc
18 - nvidia,tegra30-pmc
19 - nvidia,tegra114-pmc
[all …]
|
| /Linux-v5.15/Documentation/networking/ |
| D | regulatory.rst | 1 .. SPDX-License-Identifier: GPL-2.0
15 ---------------------------------------
19 to the kernel one regulatory domain to be used as the central
20 core regulatory domain all wireless devices should adhere to.
23 -------------------------------------------
25 When the regulatory domain is first set up, the kernel will request a
31 ---------------------------------------------------------------
33 Userspace gets a regulatory domain in the kernel by having
38 is CRDA - central regulatory domain agent. Its documented here:
43 it needs a new regulatory domain. A udev rule can be put in place
[all …]
|
| /Linux-v5.15/arch/powerpc/perf/ |
| D | hv-24x7-domains.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
4 * DOMAIN(name, num, index_kind, is_physical)
9 * @num: The number corresponding to the domain as given in
10 * documentation. We assume the catalog domain and the hcall
11 * domain have the same numbering (so far they do), but this
15 * within the given domain. Must fit the parsing rules of the
18 * @is_physical: True if the domain is physical, false otherwise (if virtual).
21 * physical core and virtual processor in 24x7 Counters specifications.
24 DOMAIN(PHYS_CHIP, 0x01, chip, true)
25 DOMAIN(PHYS_CORE, 0x02, core, true)
[all …]
|
| D | hv-24x7.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #define pr_fmt(fmt) "hv-24x7: " fmt
24 #include "hv-24x7.h"
25 #include "hv-24x7-catalog.h"
26 #include "hv-common.h"
36 static bool domain_is_valid(unsigned domain) in domain_is_valid() argument
38 switch (domain) { in domain_is_valid()
39 #define DOMAIN(n, v, x, c) \ in domain_is_valid() macro
42 #include "hv-24x7-domains.h" in domain_is_valid()
43 #undef DOMAIN in domain_is_valid()
[all …]
|
| /Linux-v5.15/Documentation/devicetree/bindings/clock/ |
| D | renesas,rzg2l-cpg.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Geert Uytterhoeven <geert+renesas@glider.be>
17 - The CPG block generates various core clocks,
18 - The Module Standby Mode block provides two functions:
19 1. Module Standby, providing a Clock Domain to control the clock supply
25 const: renesas,r9a07g044-cpg # RZ/G2{L,LC}
33 clock-names:
[all …]
|
| D | renesas,cpg-mssr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
18 - The CPG block generates various core clocks,
19 - The MSSR block provides two functions:
20 1. Module Standby, providing a Clock Domain to control the clock supply
27 - renesas,r7s9210-cpg-mssr # RZ/A2
[all …]
|
| D | qcom,sc7180-lpasscorecc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sc7180-lpasscorecc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm LPASS Core Clock Controller Binding for SC7180
10 - Taniya Das <tdas@codeaurora.org>
13 Qualcomm LPASS core clock control module which supports the clocks and
17 - dt-bindings/clock/qcom,lpasscorecc-sc7180.h
22 - qcom,sc7180-lpasshm
23 - qcom,sc7180-lpasscorecc
[all …]
|
| /Linux-v5.15/include/net/ |
| D | regulatory.h | 6 * Copyright 2008-2009 Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
25 * enum environment_cap - Environment parsed from country IE
38 * struct regulatory_request - used to keep track of regulatory requests
43 * can be used by the wireless core to deal with conflicts
49 * regulatory domain. We have a few special codes:
50 * 00 - World regulatory domain
51 * 99 - built by driver but a specific alpha2 cannot be determined
52 * 98 - result of an intersection between two regulatory domains
53 * 97 - regulatory domain has not yet been configured
54 * @dfs_region: If CRDA responded with a regulatory domain that requires
[all …]
|
| /Linux-v5.15/Documentation/devicetree/bindings/remoteproc/ |
| D | qcom,adsp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 firmware on the Qualcomm ADSP Hexagon core.
19 - qcom,msm8974-adsp-pil
20 - qcom,msm8996-adsp-pil
21 - qcom,msm8996-slpi-pil
22 - qcom,msm8998-adsp-pas
23 - qcom,msm8998-slpi-pas
[all …]
|
| D | qcom,q6v5.txt | 4 on the Qualcomm Hexagon core.
6 - compatible:
10 "qcom,q6v5-pil",
11 "qcom,ipq8074-wcss-pil"
12 "qcom,qcs404-wcss-pil"
13 "qcom,msm8916-mss-pil",
14 "qcom,msm8974-mss-pil"
15 "qcom,msm8996-mss-pil"
16 "qcom,msm8998-mss-pil"
17 "qcom,sc7180-mss-pil"
[all …]
|
| /Linux-v5.15/Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,apr.txt | 7 - compatible:
10 Definition: must be "qcom,apr-v<VERSION-NUMBER>", example "qcom,apr-v2"
12 - qcom,apr-domain
17 1 - APR simulator
18 2 - PC
19 3 - MODEM
20 4 - ADSP
21 5 - APPS
22 6 - MODEM2
23 7 - APPS2
[all …]
|
| /Linux-v5.15/Documentation/devicetree/bindings/regulator/ |
| D | nvidia,tegra-regulators-coupling.txt | 4 NVIDIA Tegra SoC's have a mandatory voltage-coupling between regulators.
9 ------------------------
11 On Tegra20 SoC's there are 3 coupled regulators: CORE, RTC and CPU.
12 The CORE and RTC voltages shall be in a range of 170mV from each other
16 ------------------------
18 On Tegra30 SoC's there are 2 coupled regulators: CORE and CPU. The CORE
19 and CPU voltages shall be in a range of 300mV from each other and CORE
24 - nvidia,tegra-core-regulator: Boolean property that designates regulator
25 as the "Core domain" voltage regulator.
26 - nvidia,tegra-rtc-regulator: Boolean property that designates regulator
[all …]
|
| D | fixed-regulator.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/fixed-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liam Girdwood <lgirdwood@gmail.com>
11 - Mark Brown <broonie@kernel.org>
14 Any property defined as part of the core regulator binding, defined in
16 expected to have the regulator-min-microvolt and regulator-max-microvolt
20 - $ref: "regulator.yaml#"
26 const: regulator-fixed-clock
[all …]
|
| /Linux-v5.15/kernel/irq/ |
| D | ipi.c | 1 // SPDX-License-Identifier: GPL-2.0
15 * irq_reserve_ipi() - Setup an IPI to destination cpumask
16 * @domain: IPI domain
23 int irq_reserve_ipi(struct irq_domain *domain, in irq_reserve_ipi() argument
30 if (!domain ||!irq_domain_is_ipi(domain)) { in irq_reserve_ipi()
31 pr_warn("Reservation on a non IPI domain\n"); in irq_reserve_ipi()
32 return -EINVAL; in irq_reserve_ipi()
37 return -EINVAL; in irq_reserve_ipi()
43 return -EINVAL; in irq_reserve_ipi()
46 if (irq_domain_is_ipi_single(domain)) { in irq_reserve_ipi()
[all …]
|
| /Linux-v5.15/arch/powerpc/platforms/powernv/ |
| D | opal-imc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include <asm/imc-pmu.h>
57 struct imc_mem_info *ptr = pmu_ptr->mem_info; in export_imc_mode_and_cmd()
64 while (ptr->vbase != NULL) { in export_imc_mode_and_cmd()
65 loc = (u64)(ptr->vbase) + cb_offset; in export_imc_mode_and_cmd()
67 sprintf(mode, "imc_mode_%d", (u32)(ptr->id)); in export_imc_mode_and_cmd()
72 sprintf(cmd, "imc_cmd_%d", (u32)(ptr->id)); in export_imc_mode_and_cmd()
91 nr_chips = of_property_count_u32_elems(node, "chip-id"); in imc_get_mem_addr_nest()
93 return -ENODEV; in imc_get_mem_addr_nest()
97 return -ENOMEM; in imc_get_mem_addr_nest()
[all …]
|
| /Linux-v5.15/Documentation/sound/soc/ |
| D | dapm.rst | 11 such, can easily co-exist with the other PM systems.
14 all power switching is done within the ASoC core. No code changes or
25 Codec bias domain
26 VREF, VMID (core codec and audio power)
31 Platform/Machine domain
38 Path domain
44 Stream domain
60 Audio DAPM widgets fall into a number of types:-
127 (Widgets are defined in include/sound/soc-dapm.h)
130 There are convenience macros defined in soc-dapm.h that can be used to quickly
[all …]
|
| /Linux-v5.15/include/linux/fsl/ |
| D | guts.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
29 u32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
30 u32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
31 u32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and
34 u32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
35 u32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
36 u32 pordevsr2; /* 0x.0014 - POR device status register 2 */
37 u8 res018[0x20 - 0x18];
38 u32 porcir; /* 0x.0020 - POR Configuration Information
41 u8 res024[0x30 - 0x24];
[all …]
|
| /Linux-v5.15/drivers/gpio/ |
| D | gpio-grgpio.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * This driver supports the GRGPIO GPIO core available in the GRLIB VHDL
8 * IP core library.
10 * Full documentation of the GRGPIO core can be found here:
13 * See "Documentation/devicetree/bindings/gpio/gpio-grgpio.txt" for
45 /* Structure for an irq of the core - called an underlying irq */
56 s8 index; /* Index into struct grgpio_priv's uirqs, or -1 */
68 * The grgpio core can have multiple "underlying" irqs. The gpio lines
70 * independently of each other. This driver sets up an irq domain and
73 struct irq_domain *domain; member
[all …]
|
| /Linux-v5.15/Documentation/devicetree/bindings/media/ |
| D | qcom,sm8250-venus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/media/qcom,sm8250-venus.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Stanimir Varbanov <stanimir.varbanov@linaro.org>
19 const: qcom,sm8250-venus
27 power-domains:
31 power-domain-names:
34 - const: venus
35 - const: vcodec0
[all …]
|
| /Linux-v5.15/drivers/soc/ti/ |
| D | ti_sci_pm_domains.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI SCI Generic Power Domain Driver
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
6 * J Keerthy <j-keerthy@ti.com>
7 * Dave Gerlach <d-gerlach@ti.com>
17 #include <dt-bindings/soc/ti,sci_pm_domain.h>
25 * @data: onecell data for genpd core
35 * struct ti_sci_pm_domain: TI specific data needed for power domain
56 * @domain: pointer to the powerdomain to power off
58 static int ti_sci_pd_power_off(struct generic_pm_domain *domain) in ti_sci_pd_power_off() argument
[all …]
|
| /Linux-v5.15/arch/x86/platform/uv/ |
| D | uv_irq.c | 37 entry->vector = cfg->vector; in uv_program_mmr()
38 entry->delivery_mode = apic->delivery_mode; in uv_program_mmr()
39 entry->dest_mode = apic->dest_mode_logical; in uv_program_mmr()
40 entry->polarity = 0; in uv_program_mmr()
41 entry->trigger = 0; in uv_program_mmr()
42 entry->mask = 0; in uv_program_mmr()
43 entry->dest = cfg->dest_apicid; in uv_program_mmr()
45 uv_write_global_mmr64(info->pnode, info->offset, mmr_value); in uv_program_mmr()
54 struct irq_data *parent = data->parent_data; in uv_set_irq_affinity()
58 ret = parent->chip->irq_set_affinity(parent, mask, force); in uv_set_irq_affinity()
[all …]
|
| /Linux-v5.15/drivers/irqchip/ |
| D | irq-loongson-liointc.c | 1 // SPDX-License-Identifier: GPL-2.0
55 struct irq_chip_generic *gc = handler->priv->gc; in liointc_chained_handle_irq()
56 int core = get_ebase_cpunum() % LIOINTC_NUM_CORES; in liointc_chained_handle_irq() local
61 pending = readl(handler->priv->core_isr[core]); in liointc_chained_handle_irq()
65 if (handler->priv->has_lpc_irq_errata && in liointc_chained_handle_irq()
66 (handler->parent_int_map & gc->mask_cache & in liointc_chained_handle_irq()
76 generic_handle_domain_irq(gc->domain, bit); in liointc_chained_handle_irq()
88 writel(readl(gc->reg_base + offset) | mask, in liointc_set_bit()
89 gc->reg_base + offset); in liointc_set_bit()
91 writel(readl(gc->reg_base + offset) & ~mask, in liointc_set_bit()
[all …]
|
