Lines Matching +full:core +full:- +full:domain
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
29 u32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
30 u32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
31 u32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and
34 u32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
35 u32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
36 u32 pordevsr2; /* 0x.0014 - POR device status register 2 */
37 u8 res018[0x20 - 0x18];
38 u32 porcir; /* 0x.0020 - POR Configuration Information
41 u8 res024[0x30 - 0x24];
42 u32 gpiocr; /* 0x.0030 - GPIO Control Register */
43 u8 res034[0x40 - 0x34];
44 u32 gpoutdr; /* 0x.0040 - General-Purpose Output Data
47 u8 res044[0x50 - 0x44];
48 u32 gpindr; /* 0x.0050 - General-Purpose Input Data
51 u8 res054[0x60 - 0x54];
52 u32 pmuxcr; /* 0x.0060 - Alternate Function Signal
55 u32 pmuxcr2; /* 0x.0064 - Alternate function signal
58 u32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
59 u8 res06c[0x70 - 0x6c];
60 u32 devdisr; /* 0x.0070 - Device Disable Control */
63 u32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
64 u8 res078[0x7c - 0x78];
65 u32 pmjcr; /* 0x.007c - 4 Power Management Jog Control
68 u32 powmgtcsr; /* 0x.0080 - Power Management Status and
71 u32 pmrccr; /* 0x.0084 - Power Management Reset Counter
74 u32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter
77 u32 pmcdr; /* 0x.008c - 4Power management clock disable
80 u32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
81 u32 rstrscr; /* 0x.0094 - Reset Request Status and
84 u32 ectrstcr; /* 0x.0098 - Exception reset control register */
85 u32 autorstsr; /* 0x.009c - Automatic reset status register */
86 u32 pvr; /* 0x.00a0 - Processor Version Register */
87 u32 svr; /* 0x.00a4 - System Version Register */
88 u8 res0a8[0xb0 - 0xa8];
89 u32 rstcr; /* 0x.00b0 - Reset Control Register */
90 u8 res0b4[0xc0 - 0xb4];
91 u32 iovselsr; /* 0x.00c0 - I/O voltage select status register
93 u8 res0c4[0x100 - 0xc4];
94 u32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers
96 u8 res140[0x224 - 0x140];
97 u32 iodelay1; /* 0x.0224 - IO delay control register 1 */
98 u32 iodelay2; /* 0x.0228 - IO delay control register 2 */
99 u8 res22c[0x604 - 0x22c];
100 u32 pamubypenr; /* 0x.604 - PAMU bypass enable register */
101 u8 res608[0x800 - 0x608];
102 u32 clkdvdr; /* 0x.0800 - Clock Divide Register */
103 u8 res804[0x900 - 0x804];
104 u32 ircr; /* 0x.0900 - Infrared Control Register */
105 u8 res904[0x908 - 0x904];
106 u32 dmacr; /* 0x.0908 - DMA Control Register */
107 u8 res90c[0x914 - 0x90c];
108 u32 elbccr; /* 0x.0914 - eLBC Control Register */
109 u8 res918[0xb20 - 0x918];
110 u32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
111 u32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
112 u32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
113 u8 resb2c[0xe00 - 0xb2c];
114 u32 clkocr; /* 0x.0e00 - Clock Out Select Register */
115 u8 rese04[0xe10 - 0xe04];
116 u32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
117 u8 rese14[0xe20 - 0xe14];
118 u32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
119 u32 cpfor; /* 0x.0e24 - L2 charge pump fuse override
122 u8 rese28[0xf04 - 0xe28];
123 u32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
124 u32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
125 u8 resf0c[0xf2c - 0xf0c];
126 u32 itcr; /* 0x.0f2c - Internal transaction control
129 u8 resf30[0xf40 - 0xf30];
130 u32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */
131 u32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
158 unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch)); in guts_set_dmacr()
160 clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift); in guts_set_dmacr()
195 unsigned int shift = 2 * (co + 1) - (ch & 1) - 1; in guts_set_pmuxcr_dma()
197 clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift); in guts_set_pmuxcr_dma()
218 __be32 cdozsr; /* 0x0004 Core Doze Status Register */
220 __be32 cdozcr; /* 0x000c Core Doze Control Register */
222 __be32 cnapsr; /* 0x0014 Core Nap Status Register */
224 __be32 cnapcr; /* 0x001c Core Nap Control Register */
226 __be32 cdozpsr; /* 0x0024 Core Doze Previous Status Register */
228 __be32 cnappsr; /* 0x002c Core Nap Previous Status Register */
230 __be32 cwaitsr; /* 0x0034 Core Wait Status Register */
232 __be32 cwdtdsr; /* 0x003c Core Watchdog Detect Status Register */
238 __be32 cpmimr; /* 0x0064 Core PM IRQ Mask Register */
240 __be32 cpmcimr; /* 0x006c Core PM Critical IRQ Mask Register */
242 __be32 cpmmcmr; /* 0x0074 Core PM Machine Check Mask Register */
244 __be32 cpmnmimr; /* 0x007c Core PM NMI Mask Register */
246 __be32 ctbenr; /* 0x0084 Core Time Base Enable Register */
248 __be32 ctbckselr; /* 0x008c Core Time Base Clock Select Register */
250 __be32 ctbhltcr; /* 0x0094 Core Time Base Halt Control Register */
252 __be32 cmcpmaskcr; /* 0x00a4 Core Machine Check Mask Register */
267 __be32 pcph15sr; /* Physical Core PH15 Status Register */
268 __be32 pcph15setr; /* Physical Core PH15 Set Control Register */
269 __be32 pcph15clrr; /* Physical Core PH15 Clear Control Register */
270 __be32 pcph15psr; /* Physical Core PH15 Prev Status Register */
272 __be32 pcph20sr; /* Physical Core PH20 Status Register */
273 __be32 pcph20setr; /* Physical Core PH20 Set Control Register */
274 __be32 pcph20clrr; /* Physical Core PH20 Clear Control Register */
275 __be32 pcph20psr; /* Physical Core PH20 Prev Status Register */
276 __be32 pcpw20sr; /* Physical Core PW20 Status Register */
278 __be32 pcph30sr; /* Physical Core PH30 Status Register */
279 __be32 pcph30setr; /* Physical Core PH30 Set Control Register */
280 __be32 pcph30clrr; /* Physical Core PH30 Clear Control Register */
281 __be32 pcph30psr; /* Physical Core PH30 Prev Status Register */
301 __be32 pctbenr; /* Physical Core Time Base Enable Reg */
302 __be32 pctbclkselr; /* Physical Core Time Base Clock Select */
310 __be32 cddslpsetr; /* Core Domain Deep Sleep Set Register */
311 __be32 cddslpclrr; /* Core Domain Deep Sleep Clear Register */
312 __be32 cdpwroksetr; /* Core Domain Power OK Set Register */
313 __be32 cdpwrokclrr; /* Core Domain Power OK Clear Register */
314 __be32 cdpwrensr; /* Core Domain Power Enable Status Register */
315 __be32 cddslsr; /* Core Domain Deep Sleep Status Register */