1 // SPDX-License-Identifier: GPL-2.0
55 	struct irq_chip_generic *gc = handler->priv->gc;  in liointc_chained_handle_irq()
56 	int core = get_ebase_cpunum() % LIOINTC_NUM_CORES;  in liointc_chained_handle_irq()  local
61 	pending = readl(handler->priv->core_isr[core]);  in liointc_chained_handle_irq()
65 		if (handler->priv->has_lpc_irq_errata &&  in liointc_chained_handle_irq()
66 			(handler->parent_int_map & gc->mask_cache &  in liointc_chained_handle_irq()
76 		generic_handle_domain_irq(gc->domain, bit);  in liointc_chained_handle_irq()
88 		writel(readl(gc->reg_base + offset) | mask,  in liointc_set_bit()
89 				gc->reg_base + offset);  in liointc_set_bit()
91 		writel(readl(gc->reg_base + offset) & ~mask,  in liointc_set_bit()
92 				gc->reg_base + offset);  in liointc_set_bit()
98 	u32 mask = data->mask;  in liointc_set_type()
121 		return -EINVAL;  in liointc_set_type()
131 	struct liointc_priv *priv = gc->private;  in liointc_resume()
137 	writel(0xffffffff, gc->reg_base + LIOINTC_REG_INTC_DISABLE);  in liointc_resume()
140 		writeb(priv->map_cache[i], gc->reg_base + i);  in liointc_resume()
142 	writel(gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE);  in liointc_resume()
152 	int index = of_property_match_string(node, "reg-names", name);  in liointc_get_reg_byname()
164 	struct irq_domain *domain;  in liointc_of_init()  local
175 		return -ENOMEM;  in liointc_of_init()
177 	if (of_device_is_compatible(node, "loongson,liointc-2.0")) {  in liointc_of_init()
180 			err = -ENODEV;  in liointc_of_init()
185 			priv->core_isr[i] = liointc_get_reg_byname(node, core_reg_names[i]);  in liointc_of_init()
186 		if (!priv->core_isr[0]) {  in liointc_of_init()
187 			err = -ENODEV;  in liointc_of_init()
193 			err = -ENODEV;  in liointc_of_init()
198 			priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS;  in liointc_of_init()
207 		err = -ENODEV;  in liointc_of_init()
217 		pr_err("loongson-liointc: No parent_int_map\n");  in liointc_of_init()
218 		err = -ENODEV;  in liointc_of_init()
223 		priv->handler[i].parent_int_map = of_parent_int_map[i];  in liointc_of_init()
225 	/* Setup IRQ domain */  in liointc_of_init()
226 	domain = irq_domain_add_linear(node, 32,  in liointc_of_init()
228 	if (!domain) {  in liointc_of_init()
229 		pr_err("loongson-liointc: cannot add IRQ domain\n");  in liointc_of_init()
230 		err = -EINVAL;  in liointc_of_init()
234 	err = irq_alloc_domain_generic_chips(domain, 32, 1,  in liointc_of_init()
235 					node->full_name, handle_level_irq,  in liointc_of_init()
238 		pr_err("loongson-liointc: unable to register IRQ domain\n");  in liointc_of_init()
250 		u32 pending = priv->handler[i].parent_int_map;  in liointc_of_init()
255 			priv->map_cache[bit] = BIT(i) << LIOINTC_SHIFT_INTx;  in liointc_of_init()
261 		/* Generate core part of map cache */  in liointc_of_init()
262 		priv->map_cache[i] |= BIT(loongson_sysconf.boot_cpu_id);  in liointc_of_init()
263 		writeb(priv->map_cache[i], base + i);  in liointc_of_init()
266 	gc = irq_get_domain_generic_chip(domain, 0);  in liointc_of_init()
267 	gc->private = priv;  in liointc_of_init()
268 	gc->reg_base = base;  in liointc_of_init()
269 	gc->domain = domain;  in liointc_of_init()
270 	gc->resume = liointc_resume;  in liointc_of_init()
272 	ct = gc->chip_types;  in liointc_of_init()
273 	ct->regs.enable = LIOINTC_REG_INTC_ENABLE;  in liointc_of_init()
274 	ct->regs.disable = LIOINTC_REG_INTC_DISABLE;  in liointc_of_init()
275 	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;  in liointc_of_init()
276 	ct->chip.irq_mask = irq_gc_mask_disable_reg;  in liointc_of_init()
277 	ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;  in liointc_of_init()
278 	ct->chip.irq_set_type = liointc_set_type;  in liointc_of_init()
280 	gc->mask_cache = 0;  in liointc_of_init()
281 	priv->gc = gc;  in liointc_of_init()
287 		priv->handler[i].priv = priv;  in liointc_of_init()
289 				liointc_chained_handle_irq, &priv->handler[i]);  in liointc_of_init()
295 	irq_domain_remove(domain);  in liointc_of_init()
298 		if (!priv->core_isr[i])  in liointc_of_init()
300 		iounmap(priv->core_isr[i]);  in liointc_of_init()
310 IRQCHIP_DECLARE(loongson_liointc_1_0, "loongson,liointc-1.0", liointc_of_init);
311 IRQCHIP_DECLARE(loongson_liointc_1_0a, "loongson,liointc-1.0a", liointc_of_init);
312 IRQCHIP_DECLARE(loongson_liointc_2_0, "loongson,liointc-2.0", liointc_of_init);