Searched +full:controller +full:- +full:number (Results 1 – 25 of 1109) sorted by relevance
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| /Linux-v6.1/Documentation/devicetree/bindings/pci/ |
| D | pci-msi.txt | 5 (AKA RID). A Requester ID is a triplet of a Bus number, Device number, and
6 Function number.
11 * Bits [15:8] are the Bus number.
12 * Bits [7:3] are the Device number.
13 * Bits [2:0] are the Function number.
23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
30 -------------------
32 - msi-map: Maps a Requester ID to an MSI controller and associated
33 msi-specifier data. The property is an arbitrary number of tuples of
34 (rid-base,msi-controller,msi-base,length), where:
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| D | ralink,rt3883-pci.txt | 1 * Mediatek/Ralink RT3883 PCI controller
7 - compatible: must be "ralink,rt3883-pci"
9 - reg: specifies the physical base address of the controller and
12 - #address-cells: specifies the number of cells needed to encode an
15 - #size-cells: specifies the number of cells used to represent the size
18 - ranges: specifies the translation between child address space and parent
23 - status: indicates the operational status of the device.
28 The main node must have two child nodes which describes the built-in
29 interrupt controller and the PCI host bridge.
31 a) Interrupt controller:
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| /Linux-v6.1/Documentation/core-api/irq/ |
| D | irq-domain.rst | 2 The irq_domain interrupt number mapping library
5 The current design of the Linux kernel uses a single large number
6 space where each separate IRQ source is assigned a different number.
7 This is simple when there is only one interrupt controller, but in
9 that each one gets assigned non-overlapping allocations of Linux
12 The number of interrupt controllers registered as unique irqchips
18 Here the interrupt number loose all kind of correspondence to
21 interrupt controller (i.e. the component actually fireing the
22 interrupt line to the CPU) nowadays this number is just a number.
24 For this reason we need a mechanism to separate controller-local
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| /Linux-v6.1/tools/perf/pmu-events/arch/x86/skylake/ |
| D | uncore-other.json | 3 …"BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture,…
8 …"PublicDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture…
13 …Number of all Core entries outstanding for the memory controller. The outstanding interval starts …
17 …Number of all Core entries outstanding for the memory controller. The outstanding interval starts …
22 …uest outstanding is waiting for data return from memory controller. Account for coherent and non-c…
27 …uest outstanding is waiting for data return from memory controller. Account for coherent and non-c…
32 …"BriefDescription": "Number of Core Data Read entries outstanding for the memory controller. The o…
36 …"PublicDescription": "Number of Core Data Read entries outstanding for the memory controller. The …
41 …"BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose da…
46 …"PublicDescription": "Number of Core coherent Data Read requests sent to memory controller whose d…
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| /Linux-v6.1/drivers/pinctrl/samsung/ |
| D | pinctrl-exynos-arm64.c | 1 // SPDX-License-Identifier: GPL-2.0+
17 #include <linux/soc/samsung/exynos-regs-pmu.h>
19 #include "pinctrl-samsung.h"
20 #include "pinctrl-exynos.h"
44 * Bank type for non-alive type. Bit fields:
64 /* pin banks of exynos5433 pin-controller - ALIVE */
66 /* Must start with EINTG banks, ordered by EINT group number. */
78 /* pin banks of exynos5433 pin-controller - AUD */
80 /* Must start with EINTG banks, ordered by EINT group number. */
85 /* pin banks of exynos5433 pin-controller - CPIF */
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| D | pinctrl-samsung.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
65 * enum eint_type - possible external interrupt types.
71 * Samsung GPIO controller groups all the available pins into banks. The pins
85 /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
116 * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
118 * @pctl_offset: starting offset of the pin-bank registers.
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| D | pinctrl-exynos-arm.c | 1 // SPDX-License-Identifier: GPL-2.0+
20 #include <linux/soc/samsung/exynos-regs-pmu.h>
22 #include "pinctrl-samsung.h"
23 #include "pinctrl-exynos.h"
35 /* Retention control for S5PV210 are located at the end of clock controller */
45 void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv; in s5pv210_retention_disable()
62 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); in s5pv210_retention_init()
64 return ERR_PTR(-ENOMEM); in s5pv210_retention_init()
66 np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock"); in s5pv210_retention_init()
68 pr_err("%s: failed to find clock controller DT node\n", in s5pv210_retention_init()
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| /Linux-v6.1/Documentation/devicetree/bindings/pinctrl/ |
| D | microchip,sparx5-sgpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microsemi/Microchip Serial GPIO controller
10 - Lars Povlsen <lars.povlsen@microchip.com>
13 By using a serial interface, the SIO controller significantly extend
14 the number of available GPIOs with a minimum number of additional
17 controller.
21 pattern: "^gpio@[0-9a-f]+$"
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| D | pinctrl-st.txt | 1 *ST pin controller.
3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
14 GPIO bank can have one of the two possible types of interrupt-wirings.
17 reduces number of overall interrupts numbers required. All these banks belong to
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
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| /Linux-v6.1/Documentation/devicetree/bindings/gpio/ |
| D | nvidia,tegra186-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra GPIO Controller (Tegra186 and later)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 Tegra186 contains two GPIO controllers; a main controller and an "AON"
15 controller. This binding document applies to both controllers. The register
20 The Tegra186 GPIO controller allows software to set the IO direction of,
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| D | gpio.txt | 5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
32 data-gpios = <&gpio1 12 0>,
42 The exact meaning of each specifier cell is controller specific, and must be
44 recommended to use the two-cell approach.
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| D | brcm,brcmstb-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB "UPG GIO" GPIO controller
10 The controller's registers are organized as sets of eight 32-bit
12 interrupt is shared for all of the banks handled by the controller.
15 - Doug Berger <opendmb@gmail.com>
16 - Florian Fainelli <f.fainelli@gmail.com>
21 - enum:
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| D | brcm,kona-gpio.txt | 7 The Broadcom GPIO Controller IP can be configured prior to synthesis to
9 GPIO controller only supports edge, not level, triggering of interrupts.
12 -------------------
14 - compatible: "brcm,bcm11351-gpio", "brcm,kona-gpio"
15 - reg: Physical base address and length of the controller's registers.
16 - interrupts: The interrupt outputs from the controller. There is one GPIO
17 interrupt per GPIO bank. The number of interrupts listed depends on the
18 number of GPIO banks on the SoC. The interrupts must be ordered by bank,
21 - #gpio-cells: Should be <2>. The first cell is the pin number, the second
23 - bit 0 specifies polarity (0 for normal, 1 for inverted)
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| /Linux-v6.1/Documentation/devicetree/bindings/input/ |
| D | samsung-keypad.txt | 1 * Samsung's Keypad Controller device tree bindings
3 Samsung's Keypad controller is used to interface a SoC with a matrix-type
4 keypad device. The keypad controller supports multiple row and column lines.
6 The keypad controller can sense a key-press and key-release and report the
10 - compatible: should be one of the following
11 - "samsung,s3c6410-keypad": For controllers compatible with s3c6410 keypad
12 controller.
13 - "samsung,s5pv210-keypad": For controllers compatible with s5pv210 keypad
14 controller.
16 - reg: physical base address of the controller and length of memory mapped
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| /Linux-v6.1/tools/perf/pmu-events/arch/x86/sandybridge/ |
| D | uncore-other.json | 3 "BriefDescription": "Cycles weighted by number of requests pending in Coherency Tracker.",
7 "PublicDescription": "Cycles weighted by number of requests pending in Coherency Tracker.",
12 "BriefDescription": "Number of requests allocated in Coherency Tracker.",
17 "PublicDescription": "Number of requests allocated in Coherency Tracker.",
22 … cycles weighted by the number of requests waiting for data returning from the memory controller. …
26 … cycles weighted by the number of requests waiting for data returning from the memory controller. …
31 …sts outstanding are waiting for data return from memory controller. Account for coherent and non-c…
37 …sts outstanding are waiting for data return from memory controller. Account for coherent and non-c…
42 …uest outstanding is waiting for data return from memory controller. Account for coherent and non-c…
48 …uest outstanding is waiting for data return from memory controller. Account for coherent and non-c…
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| /Linux-v6.1/tools/perf/pmu-events/arch/x86/ivybridge/ |
| D | uncore-other.json | 3 "BriefDescription": "Cycles weighted by number of requests pending in Coherency Tracker.",
7 "PublicDescription": "Cycles weighted by number of requests pending in Coherency Tracker.",
12 "BriefDescription": "Number of requests allocated in Coherency Tracker.",
17 "PublicDescription": "Number of requests allocated in Coherency Tracker.",
22 … cycles weighted by the number of requests waiting for data returning from the memory controller. …
26 … cycles weighted by the number of requests waiting for data returning from the memory controller. …
31 …sts outstanding are waiting for data return from memory controller. Account for coherent and non-c…
37 …sts outstanding are waiting for data return from memory controller. Account for coherent and non-c…
42 …uest outstanding is waiting for data return from memory controller. Account for coherent and non-c…
48 …uest outstanding is waiting for data return from memory controller. Account for coherent and non-c…
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| /Linux-v6.1/Documentation/devicetree/bindings/interrupt-controller/ |
| D | ti,omap2-intc.txt | 1 * OMAP Interrupt Controller
3 OMAP2/3 are using a TI interrupt controller that can support several
4 configurable number of interrupts.
8 - compatible : should be:
9 "ti,omap2-intc"
10 - interrupt-controller : Identifies the node as an interrupt controller
11 - #interrupt-cells : Specifies the number of cells needed to encode an
14 The cell contains the interrupt number in the range [0-128].
15 - ti,intc-size: Number of interrupts handled by the interrupt controller.
16 - reg: physical base address and size of the intc registers map.
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| D | ti,cp-intc.txt | 1 * TI Common Platform Interrupt Controller
3 Common Platform Interrupt Controller (cp_intc) is used on
4 OMAP-L1x SoCs and can support several configurable number
9 - compatible : should be:
10 "ti,cp-intc"
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells : Specifies the number of cells needed to encode an
15 The cell contains the interrupt number in the range [0-128].
16 - ti,intc-size: Number of interrupts handled by the interrupt controller.
17 - reg: physical base address and size of the intc registers map.
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| D | arm,versatile-fpga-irq.txt | 1 * ARM Versatile FPGA interrupt controller
9 - compatible: "arm,versatile-fpga-irq" or "oxsemi,ox810se-rps-irq"
10 - interrupt-controller: Identifies the node as an interrupt controller
11 - #interrupt-cells: The number of cells to define the interrupts. Must be 1
12 as the FPGA IRQ controller has no configuration options for interrupt
13 sources. The cell is a u32 and defines the interrupt number.
14 - reg: The register bank for the FPGA interrupt controller.
15 - clear-mask: a u32 number representing the mask written to clear all IRQs
16 on the controller at boot for example.
17 - valid-mask: a u32 number representing a bit mask determining which of
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| D | samsung,exynos4210-combiner.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/samsung,exynos4210-combiner.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC Interrupt Combiner Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 Samsung's Exynos4 architecture includes a interrupt combiner controller which
16 a parent interrupt controller, such as GIC in case of Exynos4210.
18 The interrupt combiner controller consists of multiple combiners. Up to eight
21 usually connected to a parent interrupt controller.
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| D | img,pdc-intc.txt | 1 * ImgTec Powerdown Controller (PDC) Interrupt Controller Binding
4 representation of a PDC IRQ controller. This has a number of input interrupt
10 - compatible: Specifies the compatibility list for the interrupt controller.
11 The type shall be <string> and the value shall include "img,pdc-intc".
13 - reg: Specifies the base PDC physical address(s) and size(s) of the
14 addressable register space. The type shall be <prop-encoded-array>.
16 - interrupt-controller: The presence of this property identifies the node
17 as an interrupt controller. No property value shall be defined.
19 - #interrupt-cells: Specifies the number of cells needed to encode an
22 - num-perips: Number of waking peripherals.
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| /Linux-v6.1/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpic.txt | 2 Freescale MPIC Interrupt Controller Node
6 The Freescale MPIC interrupt controller is found on all PowerQUICC
14 - compatible
22 - reg
24 Value type: <prop-encoded-array>
29 - interrupt-controller
33 controller
35 - #interrupt-cells
39 specifiers do not contain the interrupt-type or type-specific
42 - #address-cells
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| /Linux-v6.1/Documentation/devicetree/bindings/i2c/ |
| D | i2c-pxa-pci-ce4100.txt | 2 ----------
4 CE4100 has one PCI device which is described as the I2C-Controller. This
5 PCI device has three PCI-bars, each bar contains a complete I2C
6 controller. So we have a total of three independent I2C-Controllers
8 The driver is probed via the PCI-ID and is gathering the information of
10 Grant Likely recommended to use the ranges property to map the PCI-Bar
11 number to its physical address and to use this to find the child nodes
12 of the specific I2C controller. This were his exact words:
22 non-zero if you had 2 or more devices mapped off
30 ------------------------------------------------
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| /Linux-v6.1/include/linux/ |
| D | mhi.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
10 #include <linux/dma-direction.h>
27 * enum mhi_callback - MHI callback
51 * enum mhi_flags - Transfer flags
63 * enum mhi_device_type - Device types
73 * enum mhi_ch_type - Channel types
89 * struct image_info - Firmware and RDDM table
102 * struct mhi_link_info - BW requirement
103 * target_link_speed - Link speed as defined by TLS bits in LinkControl reg
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| /Linux-v6.1/drivers/usb/usbip/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
17 be called usbip-core.
25 This enables the USB/IP virtual host controller driver,
29 module will be called vhci-hcd.
32 int "Number of ports per USB/IP virtual host controller"
37 To increase number of ports available for USB/IP virtual
38 host controller driver, this defines number of ports per
39 USB/IP virtual host controller.
42 int "Number of USB/IP virtual host controllers"
47 To increase number of ports available for USB/IP virtual
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