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/Linux-v5.15/Documentation/devicetree/bindings/clock/ti/
Ddra7-atl.txt1 Device Tree Clock bindings for ATL (Audio Tracking Logic) of DRA7 SoC.
5 functional clock but can be configured to provide different clocks.
7 signals - can compensate the drift between the two ws signal.
9 In order to provide the support for ATL and it's output clocks (which can be used
10 internally within the SoC or external components) two sets of bindings is needed:
14 To be able to integrate the ATL clocks with DT clock tree.
15 Provides ccf level representation of the ATL clocks to be used by drivers.
20 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
23 - compatible : shall be "ti,dra7-atl-clock"
24 - #clock-cells : from common clock binding; shall be set to 0.
[all …]
Dcomposite.txt3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped composite clock with multiple different sub-types;
16 The binding must provide a list of the component clocks that shall be
17 merged to this clock. The component clocks shall be of one of the
18 "ti,*composite*-clock" types.
20 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
21 [2] Documentation/devicetree/bindings/clock/ti/mux.txt
22 [3] Documentation/devicetree/bindings/clock/ti/divider.txt
23 [4] Documentation/devicetree/bindings/clock/ti/gate.txt
26 - compatible : shall be: "ti,composite-clock"
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/Linux-v5.15/Documentation/devicetree/bindings/mfd/
Dcanaan,k210-sysctl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/canaan,k210-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Canaan Kendryte K210 System Controller Device Tree Bindings
10 - Damien Le Moal <damien.lemoal@wdc.com>
14 register map for controlling the clocks, reset signals and pin power
20 - const: canaan,k210-sysctl
21 - const: syscon
22 - const: simple-mfd
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/Linux-v5.15/Documentation/devicetree/bindings/soc/mediatek/
Dscpsys.txt10 The driver implements the Generic PM domain bindings described in
11 power/power-domain.yaml. It provides the power domains defined in
12 - include/dt-bindings/power/mt8173-power.h
13 - include/dt-bindings/power/mt6797-power.h
14 - include/dt-bindings/power/mt6765-power.h
15 - include/dt-bindings/power/mt2701-power.h
16 - include/dt-bindings/power/mt2712-power.h
17 - include/dt-bindings/power/mt7622-power.h
20 - compatible: Should be one of:
21 - "mediatek,mt2701-scpsys"
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/Linux-v5.15/Documentation/devicetree/bindings/clock/
Dmaxim,max77686.txt3 This is a part of device tree bindings of MAX77686/MAX77802/MAX77620
4 multi-function device. More information can be found in MFD DT binding
6 bindings/mfd/max77686.txt for MAX77686 and
7 bindings/mfd/max77802.txt for MAX77802 and
8 bindings/mfd/max77620.txt for MAX77620.
11 (gated/ungated) over I2C. Clocks are defined as preprocessor macros in
12 dt-bindings/clock/maxim,max77686.h.
16 (gated/ungated) over I2C. Clocks are defined as preprocessor macros in
17 dt-bindings/clock/maxim,max77802.h.
20 (gated/ungated) over I2C. Clocks are defined as preprocessor macros in
[all …]
Dsamsung,s5pv210-clock.txt9 - compatible: should be one of following:
10 - "samsung,s5pv210-clock" : for clock controller of Samsung
12 - "samsung,s5p6442-clock" : for clock controller of Samsung
15 - reg: physical base address of the controller and length of memory mapped
18 - #clock-cells: should be 1.
20 All available clocks are defined as preprocessor macros in
21 dt-bindings/clock/s5pv210.h header and can be used in device tree sources.
23 External clocks:
25 There are several clocks that are generated outside the SoC. It is expected
26 that they are defined using standard clock bindings with following
[all …]
Dimx8qxp-lpcg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings
10 - Aisheng Dong <aisheng.dong@nxp.com>
13 The Low-Power Clock Gate (LPCG) modules contain a local programming
15 is used to locally gate the clocks for the associated peripheral.
17 This level of clock gating is provided after the clocks are generated
23 ID in its "clocks" phandle cell. See the full list of clock IDs from:
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Dqcom,sc7180-lpasscorecc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sc7180-lpasscorecc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Taniya Das <tdas@codeaurora.org>
13 Qualcomm LPASS core clock control module which supports the clocks and
17 - dt-bindings/clock/qcom,lpasscorecc-sc7180.h
22 - qcom,sc7180-lpasshm
23 - qcom,sc7180-lpasscorecc
25 clocks:
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Dxlnx,zynqmp-clk.txt1 --------------------------------------------------------------------------
2 Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
4 --------------------------------------------------------------------------
7 as clock provider for all clock consumers of PS clocks.
9 See clock_bindings.txt for more information on the generic clock bindings.
12 - #clock-cells: Must be 1
13 - compatible: Must contain: "xlnx,zynqmp-clk"
14 - clocks: List of clock specifiers which are external input
15 clocks to the given clock controller. Please refer
16 the next section to find the input clocks for a
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Dsamsung,s3c2412-clock.txt9 - compatible: should be "samsung,s3c2412-clock"
10 - reg: physical base address of the controller and length of memory mapped
12 - #clock-cells: should be 1.
15 to specify the clock which they consume. Some of the clocks are available only
18 All available clocks are defined as preprocessor macros in
19 dt-bindings/clock/s3c2412.h header and can be used in device
22 External clocks:
24 There are several clocks that are generated outside the SoC. It is expected
25 that they are defined using standard clock bindings with following
26 clock-output-names:
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Dcanaan,k210-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/canaan,k210-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Canaan Kendryte K210 Clock Device Tree Bindings
10 - Damien Le Moal <damien.lemoal@wdc.com>
13 Canaan Kendryte K210 SoC clocks driver bindings. The clock
18 - dt-bindings/clock/k210-clk.h
22 const: canaan,k210-clk
24 clocks:
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Dqcom,gpucc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Taniya Das <tdas@codeaurora.org>
13 Qualcomm graphics clock control module which supports the clocks, resets and
17 dt-bindings/clock/qcom,gpucc-sdm845.h
18 dt-bindings/clock/qcom,gpucc-sc7180.h
19 dt-bindings/clock/qcom,gpucc-sc7280.h
20 dt-bindings/clock/qcom,gpucc-sm8150.h
21 dt-bindings/clock/qcom,gpucc-sm8250.h
[all …]
Drenesas,rzg2l-cpg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Geert Uytterhoeven <geert+renesas@glider.be>
17 - The CPG block generates various core clocks,
18 - The Module Standby Mode block provides two functions:
25 const: renesas,r9a07g044-cpg # RZ/G2{L,LC}
30 clocks:
33 clock-names:
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Dqcom,videocc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Taniya Das <tdas@codeaurora.org>
13 Qualcomm video clock control module which supports the clocks, resets and
17 dt-bindings/clock/qcom,videocc-sc7180.h
18 dt-bindings/clock/qcom,videocc-sc7280.h
19 dt-bindings/clock/qcom,videocc-sdm845.h
20 dt-bindings/clock/qcom,videocc-sm8150.h
21 dt-bindings/clock/qcom,videocc-sm8250.h
[all …]
Dsamsung,s2mps11.txt4 This is a part of device tree bindings for S2M and S5M family multi-function
6 More information can be found in bindings/mfd/sec-core.txt file.
11 To register these as clocks with common clock framework instantiate under
12 main device node a sub-node named "clocks".
15 - Documentation/devicetree/bindings/clock/clock-bindings.txt
18 Required properties of the "clocks" sub-node:
19 - #clock-cells: should be 1.
20 - compatible: Should be one of: "samsung,s2mps11-clk", "samsung,s2mps13-clk",
21 "samsung,s2mps14-clk", "samsung,s5m8767-clk"
23 clocks.
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra20-host1x.txt4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 For pre-Tegra186, one entry describing the whole register area.
7 For Tegra186, one entry for each entry in reg-names:
8 "vm" - VM region assigned to Linux
9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
10 - interrupts: The interrupt outputs from the controller.
11 - #address-cells: The number of cells used to represent physical base addresses
13 - #size-cells: The number of cells used to represent the size of an address
15 - ranges: The mapping of the host1x address space to the CPU address space.
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/Linux-v5.15/Documentation/devicetree/bindings/soc/bcm/
Dbrcm,bcm2835-pm.txt4 a watchdog timer. This binding supersedes the brcm,bcm2835-pm-wdt
9 - compatible: Should be "brcm,bcm2835-pm"
10 - reg: Specifies base physical address and size of the two
13 - clocks: a) v3d: The V3D clock from CPRMAN
17 - #reset-cells: Should be 1. This property follows the reset controller
18 bindings[1].
19 - #power-domain-cells: Should be 1. This property follows the power domain
20 bindings[2].
24 - timeout-sec: Contains the watchdog timeout in seconds
25 - system-power-controller: Whether the watchdog is controlling the
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/Linux-v5.15/Documentation/devicetree/bindings/arm/
Dsp810.txt2 -----------------------
6 - compatible: standard compatible string for a Primecell peripheral,
7 see Documentation/devicetree/bindings/arm/primecell.yaml
11 - reg: standard registers property, physical address and size
14 - clock-names: from the common clock bindings, for more details see
15 Documentation/devicetree/bindings/clock/clock-bindings.txt;
18 - clocks: from the common clock bindings, phandle and clock
19 specifier pairs for the entries of clock-names property
21 - #clock-cells: from the common clock bindings;
24 - clock-output-names: from the common clock bindings;
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/Linux-v5.15/Documentation/devicetree/bindings/media/
Dmediatek-mdp.txt6 - compatible: "mediatek,mt8173-mdp"
7 - mediatek,vpu: the node of video processor unit, see
8 Documentation/devicetree/bindings/media/mediatek-vpu.txt for details.
11 - compatible: Should be one of
12 "mediatek,mt8173-mdp-rdma" - read DMA
13 "mediatek,mt8173-mdp-rsz" - resizer
14 "mediatek,mt8173-mdp-wdma" - write DMA
15 "mediatek,mt8173-mdp-wrot" - write DMA with rotation
16 - reg: Physical base address and length of the function block register space
17 - clocks: device clocks, see
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/display/msm/
Dmdp5.txt5 This is the bindings documentation for the Mobile Display Subsytem(MDSS) that
6 encapsulates sub-blocks like MDP5, DSI, HDMI, eDP etc, and the MDP5 display
11 - compatible:
12 * "qcom,mdss" - MDSS
13 - reg: Physical base address and length of the controller's registers.
14 - reg-names: The names of register regions. The following regions are required:
17 - interrupts: The interrupt signal from MDSS.
18 - interrupt-controller: identifies the node as an interrupt controller.
19 - #interrupt-cells: specifies the number of cells needed to encode an interrupt
21 - power-domains: a power domain consumer specifier according to
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/rtc/
Dst,stm32-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/st,stm32-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Real Time Clock Bindings
10 - Gabriel Fernandez <gabriel.fernandez@st.com>
15 - st,stm32-rtc
16 - st,stm32h7-rtc
17 - st,stm32mp1-rtc
22 clocks:
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/power/
Dmediatek,power-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Weiyi Lu <weiyi.lu@mediatek.com>
11 - Matthias Brugger <mbrugger@suse.com>
17 IP cores belonging to a power domain should contain a 'power-domains'
22 const: power-controller
26 - mediatek,mt8167-power-controller
27 - mediatek,mt8173-power-controller
[all …]
Drockchip,power-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/rockchip,power-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
18 Power domains contained within power-controller node are
20 Documentation/devicetree/bindings/power/power-domain.yaml.
23 "power-domains" property that is a phandle for the
28 const: power-controller
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/phy/
Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
18 - ti,am64-wiz-10g
20 power-domains:
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/display/
Darm,komeda.txt1 Device Tree bindings for Arm Komeda display driver
4 - compatible: Should be "arm,mali-d71"
5 - reg: Physical base address and length of the registers in the system
6 - interrupts: the interrupt line number of the device in the system
7 - clocks: A list of phandle + clock-specifier pairs, one for each entry
8 in 'clock-names'
9 - clock-names: A list of clock names. It should contain:
10 - "aclk": for the main processor clock
11 - #address-cells: Must be 1
12 - #size-cells: Must be 0
[all …]

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