Lines Matching +full:clocks +full:- +full:bindings
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Weiyi Lu <weiyi.lu@mediatek.com>
11 - Matthias Brugger <mbrugger@suse.com>
17 IP cores belonging to a power domain should contain a 'power-domains'
22 const: power-controller
26 - mediatek,mt8167-power-controller
27 - mediatek,mt8173-power-controller
28 - mediatek,mt8183-power-controller
29 - mediatek,mt8192-power-controller
31 '#power-domain-cells':
34 '#address-cells':
37 '#size-cells':
41 "^power-domain@[0-9a-f]+$":
45 in Documentation/devicetree/bindings/power/power-domain.yaml.
49 '#power-domain-cells':
54 '#address-cells':
57 '#size-cells':
63 "include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain.
64 "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.
65 "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.
66 "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.
69 clocks:
71 A number of phandles to clocks that need to be enabled during domain
72 power-up sequencing.
74 clock-names:
76 List of names of clocks, in order to match the power-up sequencing
77 for each power domain we need to group the clocks by name. BASIC
78 clocks need to be enabled before enabling the corresponding power
79 domain, and should not have a '-' in their name (i.e mm, mfg, venc).
80 SUSBYS clocks need to be enabled before releasing the bus protection,
81 and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
83 In order to follow properly the power-up sequencing, the clocks must
84 be specified by order, adding first the BASIC clocks followed by the
85 SUSBSYS clocks.
87 domain-supply:
99 "^power-domain@[0-9a-f]+$":
106 '#power-domain-cells':
111 '#address-cells':
114 '#size-cells':
120 clocks:
122 A number of phandles to clocks that need to be enabled during domain
123 power-up sequencing.
125 clock-names:
127 List of names of clocks, in order to match the power-up sequencing
128 for each power domain we need to group the clocks by name. BASIC
129 clocks need to be enabled before enabling the corresponding power
130 domain, and should not have a '-' in their name (i.e mm, mfg, venc).
131 SUSBYS clocks need to be enabled before releasing the bus protection,
132 and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
134 In order to follow properly the power-up sequencing, the clocks must
135 be specified by order, adding first the BASIC clocks followed by the
136 SUSBSYS clocks.
138 domain-supply:
150 "^power-domain@[0-9a-f]+$":
157 '#power-domain-cells':
162 '#address-cells':
165 '#size-cells':
171 clocks:
173 A number of phandles to clocks that need to be enabled during domain
174 power-up sequencing.
176 clock-names:
178 List of names of clocks, in order to match the power-up sequencing
179 for each power domain we need to group the clocks by name. BASIC
180 clocks need to be enabled before enabling the corresponding power
181 domain, and should not have a '-' in their name (i.e mm, mfg, venc).
182 SUSBYS clocks need to be enabled before releasing the bus protection,
183 and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
185 In order to follow properly the power-up sequencing, the clocks must
186 be specified by order, adding first the BASIC clocks followed by the
187 SUSBSYS clocks.
189 domain-supply:
201 - reg
206 - reg
211 - reg
216 - compatible
221 - |
222 #include <dt-bindings/clock/mt8173-clk.h>
223 #include <dt-bindings/power/mt8173-power.h>
226 #address-cells = <2>;
227 #size-cells = <2>;
230 compatible = "syscon", "simple-mfd";
233 spm: power-controller {
234 compatible = "mediatek,mt8173-power-controller";
235 #address-cells = <1>;
236 #size-cells = <0>;
237 #power-domain-cells = <1>;
240 power-domain@MT8173_POWER_DOMAIN_VDEC {
242 clocks = <&topckgen CLK_TOP_MM_SEL>;
243 clock-names = "mm";
244 #power-domain-cells = <0>;
246 power-domain@MT8173_POWER_DOMAIN_VENC {
248 clocks = <&topckgen CLK_TOP_MM_SEL>,
250 clock-names = "mm", "venc";
251 #power-domain-cells = <0>;
253 power-domain@MT8173_POWER_DOMAIN_ISP {
255 clocks = <&topckgen CLK_TOP_MM_SEL>;
256 clock-names = "mm";
257 #power-domain-cells = <0>;
259 power-domain@MT8173_POWER_DOMAIN_MM {
261 clocks = <&topckgen CLK_TOP_MM_SEL>;
262 clock-names = "mm";
263 #power-domain-cells = <0>;
266 power-domain@MT8173_POWER_DOMAIN_VENC_LT {
268 clocks = <&topckgen CLK_TOP_MM_SEL>,
270 clock-names = "mm", "venclt";
271 #power-domain-cells = <0>;
273 power-domain@MT8173_POWER_DOMAIN_AUDIO {
275 #power-domain-cells = <0>;
277 power-domain@MT8173_POWER_DOMAIN_USB {
279 #power-domain-cells = <0>;
281 power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
283 clocks = <&clk26m>;
284 clock-names = "mfg";
285 #address-cells = <1>;
286 #size-cells = <0>;
287 #power-domain-cells = <1>;
289 power-domain@MT8173_POWER_DOMAIN_MFG_2D {
291 #address-cells = <1>;
292 #size-cells = <0>;
293 #power-domain-cells = <1>;
295 power-domain@MT8173_POWER_DOMAIN_MFG {
297 #power-domain-cells = <0>;