Lines Matching +full:clocks +full:- +full:bindings
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings
10 - Aisheng Dong <aisheng.dong@nxp.com>
13 The Low-Power Clock Gate (LPCG) modules contain a local programming
15 is used to locally gate the clocks for the associated peripheral.
17 This level of clock gating is provided after the clocks are generated
23 ID in its "clocks" phandle cell. See the full list of clock IDs from:
24 include/dt-bindings/clock/imx8-lpcg.h
29 - const: fsl,imx8qxp-lpcg
30 - items:
31 - enum:
32 - fsl,imx8qm-lpcg
33 - const: fsl,imx8qxp-lpcg
34 - enum:
35 - fsl,imx8qxp-lpcg-adma
36 - fsl,imx8qxp-lpcg-conn
37 - fsl,imx8qxp-lpcg-dc
38 - fsl,imx8qxp-lpcg-dsp
39 - fsl,imx8qxp-lpcg-gpu
40 - fsl,imx8qxp-lpcg-hsio
41 - fsl,imx8qxp-lpcg-img
42 - fsl,imx8qxp-lpcg-lsio
43 - fsl,imx8qxp-lpcg-vpu
48 '#clock-cells':
51 clocks:
53 Input parent clocks phandle array for each clock
57 clock-indices:
60 Refer to <include/dt-bindings/clock/imx8-lpcg.h> for the
65 clock-output-names:
69 as the clock-indices property.
73 power-domains:
77 - compatible
78 - reg
79 - '#clock-cells'
84 - |
85 #include <dt-bindings/clock/imx8-lpcg.h>
86 #include <dt-bindings/firmware/imx/rsrc.h>
87 #include <dt-bindings/interrupt-controller/arm-gic.h>
89 sdhc0_lpcg: clock-controller@5b200000 {
90 compatible = "fsl,imx8qxp-lpcg";
92 #clock-cells = <1>;
93 clocks = <&sdhc0_clk IMX_SC_PM_CLK_PER>,
96 clock-indices = <IMX_LPCG_CLK_0>,
99 clock-output-names = "sdhc0_lpcg_per_clk",
102 power-domains = <&pd IMX_SC_R_SDHC_0>;
106 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
109 clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>,
112 clock-names = "ipg", "ahb", "per";
113 power-domains = <&pd IMX_SC_R_SDHC_0>;