Searched +full:clock +full:- +full:controller (Results 1 – 25 of 1106) sorted by relevance
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| /Linux-v5.15/drivers/clk/qcom/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
14 tristate "Support for Qualcomm's clock controllers"
40 tristate "MSM8916 APCS Clock Controller"
43 Support for the APCS Clock Controller on msm8916 devices. The
49 tristate "MSM8996 CPU Clock Controller"
53 Support for the CPU clock controller on msm8996 devices.
54 Say Y if you want to support CPU clock scaling using CPUfreq
58 tristate "SDX55 APCS Clock Controller"
61 Support for the APCS Clock Controller on SDX55 platform. The
67 tristate "RPM based Clock Controller"
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| /Linux-v5.15/Documentation/devicetree/bindings/clock/ |
| D | exynos5433-clock.txt | 1 * Samsung Exynos5433 CMU (Clock Management Units)
3 The Exynos5433 clock controller generates and supplies clock to various
8 - compatible: should be one of the following.
9 - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
12 - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF
14 - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
15 which generates clocks for DRAM Memory Controller domain.
16 - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
18 - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
20 - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
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| D | exynos5260-clock.txt | 1 * Samsung Exynos5260 Clock Controller
3 Exynos5260 has 13 clock controllers which are instantiated
4 independently from the device-tree. These clock controllers
8 Each clock is assigned an identifier and client nodes can use
9 this identifier to specify the clock which they consume. All
11 dt-bindings/clock/exynos5260-clk.h header and can be used in
17 is expected that they are defined using standard clock bindings
18 with following clock-output-names:
20 - "fin_pll" - PLL input clock from XXTI
21 - "xrtcxti" - input clock from XRTCXTI
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| D | exynos7-clock.txt | 1 * Samsung Exynos7 Clock Controller
3 Exynos7 clock controller has various blocks which are instantiated
4 independently from the device-tree. These clock controllers
8 Each clock is assigned an identifier and client nodes can use
9 this identifier to specify the clock which they consume. All
11 dt-bindings/clock/exynos7-clk.h header and can be used in
17 is expected that they are defined using standard clock bindings
18 with following clock-output-names:
20 - "fin_pll" - PLL input clock from XXTI
22 Required Properties for Clock Controller:
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| D | pistachio-clock.txt | 1 Imagination Technologies Pistachio SoC clock controllers
4 Pistachio has four clock controllers (core clock, peripheral clock, peripheral
6 from the device-tree.
9 ----------------
11 There are three external inputs to the clock controllers which should be
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
17 Core clock controller:
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| D | samsung,s3c2443-clock.txt | 1 * Samsung S3C2443 Clock Controller
3 The S3C2443 clock controller generates and supplies clock to various controllers
4 within the SoC. The clock binding described here is applicable to all SoCs in
9 - compatible: should be one of the following.
10 - "samsung,s3c2416-clock" - controller compatible with S3C2416 SoC.
11 - "samsung,s3c2443-clock" - controller compatible with S3C2443 SoC.
12 - "samsung,s3c2450-clock" - controller compatible with S3C2450 SoC.
13 - reg: physical base address of the controller and length of memory mapped
15 - #clock-cells: should be 1.
17 Each clock is assigned an identifier and client nodes can use this identifier
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| D | samsung,s3c2410-clock.txt | 1 * Samsung S3C2410 Clock Controller
3 The S3C2410 clock controller generates and supplies clock to various controllers
4 within the SoC. The clock binding described here is applicable to the s3c2410,
9 - compatible: should be one of the following.
10 - "samsung,s3c2410-clock" - controller compatible with S3C2410 SoC.
11 - "samsung,s3c2440-clock" - controller compatible with S3C2440 SoC.
12 - "samsung,s3c2442-clock" - controller compatible with S3C2442 SoC.
13 - reg: physical base address of the controller and length of memory mapped
15 - #clock-cells: should be 1.
17 Each clock is assigned an identifier and client nodes can use this identifier
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| D | nuvoton,npcm750-clk.txt | 1 * Nuvoton NPCM7XX Clock Controller
3 Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
10 clk_sysbypck are inputs to the clock controller.
12 network. They are set on the device tree, but not used by the clock module. The
17 dt-bindings/clock/nuvoton,npcm7xx-clock.h
20 Required Properties of clock controller:
22 - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
25 - reg: physical base address of the clock controller and length of
28 - #clock-cells: should be 1.
30 Example: Clock controller node:
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| D | samsung,s3c64xx-clock.txt | 1 * Samsung S3C64xx Clock Controller
3 The S3C64xx clock controller generates and supplies clock to various controllers
4 within the SoC. The clock binding described here is applicable to all SoCs in
9 - compatible: should be one of the following.
10 - "samsung,s3c6400-clock" - controller compatible with S3C6400 SoC.
11 - "samsung,s3c6410-clock" - controller compatible with S3C6410 SoC.
13 - reg: physical base address of the controller and length of memory mapped
16 - #clock-cells: should be 1.
18 Each clock is assigned an identifier and client nodes can use this identifier
19 to specify the clock which they consume. Some of the clocks are available only
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| D | samsung,s5pv210-clock.txt | 1 * Samsung S5P6442/S5PC110/S5PV210 Clock Controller
3 Samsung S5P6442, S5PC110 and S5PV210 SoCs contain integrated clock
4 controller, which generates and supplies clock to various controllers
9 - compatible: should be one of following:
10 - "samsung,s5pv210-clock" : for clock controller of Samsung
12 - "samsung,s5p6442-clock" : for clock controller of Samsung
15 - reg: physical base address of the controller and length of memory mapped
18 - #clock-cells: should be 1.
21 dt-bindings/clock/s5pv210.h header and can be used in device tree sources.
26 that they are defined using standard clock bindings with following
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| D | exynos5410-clock.txt | 1 * Samsung Exynos5410 Clock Controller
3 The Exynos5410 clock controller generates and supplies clock to various
8 - compatible: should be "samsung,exynos5410-clock"
10 - reg: physical base address of the controller and length of memory mapped
13 - #clock-cells: should be 1.
15 - clocks: should contain an entry specifying the root clock from external
16 oscillator supplied through XXTI or XusbXTI pin. This clock should be
17 defined using standard clock bindings with "fin_pll" clock-output-name.
18 That clock is being passed internally to the 9 PLLs.
21 dt-bindings/clock/exynos5410.h header and can be used in device
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| D | samsung,s3c2412-clock.txt | 1 * Samsung S3C2412 Clock Controller
3 The S3C2412 clock controller generates and supplies clock to various controllers
4 within the SoC. The clock binding described here is applicable to the s3c2412
9 - compatible: should be "samsung,s3c2412-clock"
10 - reg: physical base address of the controller and length of memory mapped
12 - #clock-cells: should be 1.
14 Each clock is assigned an identifier and client nodes can use this identifier
15 to specify the clock which they consume. Some of the clocks are available only
19 dt-bindings/clock/s3c2412.h header and can be used in device
25 that they are defined using standard clock bindings with following
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| D | rockchip,rk3128-cru.txt | 1 * Rockchip RK3126/RK3128 Clock and Reset Unit
3 The RK3126/RK3128 clock controller generates and supplies clock to various
4 controllers within the SoC and also implements a reset controller for SoC
9 - compatible: should be "rockchip,rk3126-cru" or "rockchip,rk3128-cru"
10 "rockchip,rk3126-cru" - controller compatible with RK3126 SoC.
11 "rockchip,rk3128-cru" - controller compatible with RK3128 SoC.
12 - reg: physical base address of the controller and length of memory mapped
14 - #clock-cells: should be 1.
15 - #reset-cells: should be 1.
19 - rockchip,grf: phandle to the syscon managing the "general register files"
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| D | rockchip,px30-cru.txt | 1 * Rockchip PX30 Clock and Reset Unit
3 The PX30 clock controller generates and supplies clock to various
4 controllers within the SoC and also implements a reset controller for SoC
9 - compatible: PMU for CRU should be "rockchip,px30-pmu-cru"
10 - compatible: CRU should be "rockchip,px30-cru"
11 - reg: physical base address of the controller and length of memory mapped
13 - clocks: A list of phandle + clock-specifier pairs for the clocks listed
14 in clock-names
15 - clock-names: Should contain the following:
16 - "xin24m" for both PMUCRU and CRU
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| /Linux-v5.15/drivers/clk/samsung/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
4 bool "Samsung Exynos clock controller support" if COMPILE_TEST
16 bool "Samsung S3C64xx clock controller support" if COMPILE_TEST
19 Support for the clock controller present on the Samsung S3C64xx SoCs.
23 bool "Samsung S5Pv210 clock controller support" if COMPILE_TEST
26 Support for the clock controller present on the Samsung S5Pv210 SoCs.
30 bool "Samsung Exynos3250 clock controller support" if COMPILE_TEST
33 Support for the clock controller present on the Samsung
37 bool "Samsung Exynos4 clock controller support" if COMPILE_TEST
40 Support for the clock controller present on the Samsung
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| /Linux-v5.15/Documentation/devicetree/bindings/arm/mediatek/ |
| D | mediatek,mt8192-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: MediaTek Functional Clock Controller for MT8192
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
13 The Mediatek functional clock controller provides various clocks on MT8192.
18 - enum:
19 - mediatek,mt8192-scp_adsp
20 - mediatek,mt8192-imp_iic_wrap_c
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| /Linux-v5.15/drivers/clk/rockchip/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
2 # common clock support for ROCKCHIP SoC family.
5 bool "Rockchip clock controller common support"
9 Say y here to enable common clock controller for Rockchip platforms.
13 bool "Rockchip PX30 clock controller support"
17 Build the driver for PX30 Clock Driver.
20 bool "Rockchip RV110x clock controller support"
24 Build the driver for RV110x Clock Driver.
27 bool "Rockchip RK3036 clock controller support"
31 Build the driver for RK3036 Clock Driver.
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| /Linux-v5.15/arch/arm/boot/dts/ |
| D | hisi-x5hd2.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2014 Linaro Ltd.
4 * Copyright (c) 2013-2014 HiSilicon Limited.
7 #include <dt-bindings/clock/hix5hd2-clock.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
17 gic: interrupt-controller@f8a01000 {
18 compatible = "arm,cortex-a9-gic";
19 #interrupt-cells = <3>;
20 #address-cells = <0>;
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| D | hi3620.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012-2013 HiSilicon Ltd.
6 * Copyright (C) 2012-2013 Linaro Ltd.
11 #include <dt-bindings/clock/hi3620-clock.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <26000000>;
29 clock-output-names = "apb_pclk";
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| /Linux-v5.15/arch/arm64/boot/dts/freescale/ |
| D | imx8-ss-lsio.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
11 compatible = "simple-bus";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 lsio_mem_clk: clock-lsio-mem {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
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| /Linux-v5.15/include/soc/canaan/ |
| D | k210-sysctl.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
10 * Kendryte K210 SoC system controller registers offsets.
11 * Taken from Kendryte SDK (kendryte-standalone-sdk).
15 #define K210_SYSCTL_PLL0 0x08 /* PLL0 controller */
16 #define K210_SYSCTL_PLL1 0x0C /* PLL1 controller */
17 #define K210_SYSCTL_PLL2 0x10 /* PLL2 controller */
20 #define K210_SYSCTL_SEL0 0x20 /* Clock select controller 0 */
21 #define K210_SYSCTL_SEL1 0x24 /* Clock select controller 1 */
22 #define K210_SYSCTL_EN_CENT 0x28 /* Central clock enable */
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| /Linux-v5.15/arch/arm64/boot/dts/hisilicon/ |
| D | hi3670.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/hi3670-clock.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <2>;
25 #size-cells = <0>;
27 cpu-map {
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| /Linux-v5.15/Documentation/devicetree/bindings/display/tegra/ |
| D | nvidia,tegra20-host1x.txt | 4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 For pre-Tegra186, one entry describing the whole register area.
7 For Tegra186, one entry for each entry in reg-names:
8 "vm" - VM region assigned to Linux
9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
10 - interrupts: The interrupt outputs from the controller.
11 - #address-cells: The number of cells used to represent physical base addresses
13 - #size-cells: The number of cells used to represent the size of an address
15 - ranges: The mapping of the host1x address space to the CPU address space.
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| /Linux-v5.15/arch/arm64/boot/dts/mediatek/ |
| D | mt6779.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
8 #include <dt-bindings/clock/mt6779-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/mt6779-pinfunc.h>
15 interrupt-parent = <&sysirq>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 compatible = "arm,psci-0.2";
25 #address-cells = <1>;
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| /Linux-v5.15/arch/arm64/boot/dts/lg/ |
| D | lg1312.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <0>;
24 compatible = "arm,cortex-a53";
26 next-level-cache = <&L2_0>;
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