Lines Matching +full:clock +full:- +full:controller
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
11 compatible = "simple-bus";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 lsio_mem_clk: clock-lsio-mem {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
19 clock-frequency = <200000000>;
20 clock-output-names = "lsio_mem_clk";
23 lsio_bus_clk: clock-lsio-bus {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <100000000>;
27 clock-output-names = "lsio_bus_clk";
33 gpio-controller;
34 #gpio-cells = <2>;
35 interrupt-controller;
36 #interrupt-cells = <2>;
37 power-domains = <&pd IMX_SC_R_GPIO_0>;
43 gpio-controller;
44 #gpio-cells = <2>;
45 interrupt-controller;
46 #interrupt-cells = <2>;
47 power-domains = <&pd IMX_SC_R_GPIO_1>;
53 gpio-controller;
54 #gpio-cells = <2>;
55 interrupt-controller;
56 #interrupt-cells = <2>;
57 power-domains = <&pd IMX_SC_R_GPIO_2>;
63 gpio-controller;
64 #gpio-cells = <2>;
65 interrupt-controller;
66 #interrupt-cells = <2>;
67 power-domains = <&pd IMX_SC_R_GPIO_3>;
73 gpio-controller;
74 #gpio-cells = <2>;
75 interrupt-controller;
76 #interrupt-cells = <2>;
77 power-domains = <&pd IMX_SC_R_GPIO_4>;
83 gpio-controller;
84 #gpio-cells = <2>;
85 interrupt-controller;
86 #interrupt-cells = <2>;
87 power-domains = <&pd IMX_SC_R_GPIO_5>;
93 gpio-controller;
94 #gpio-cells = <2>;
95 interrupt-controller;
96 #interrupt-cells = <2>;
97 power-domains = <&pd IMX_SC_R_GPIO_6>;
103 gpio-controller;
104 #gpio-cells = <2>;
105 interrupt-controller;
106 #interrupt-cells = <2>;
107 power-domains = <&pd IMX_SC_R_GPIO_7>;
113 #mbox-cells = <2>;
120 #mbox-cells = <2>;
126 #mbox-cells = <2>;
133 #mbox-cells = <2>;
140 #mbox-cells = <2>;
147 #mbox-cells = <2>;
148 power-domains = <&pd IMX_SC_R_MU_13A>;
152 pwm0_lpcg: clock-controller@5d400000 {
153 compatible = "fsl,imx8qxp-lpcg";
155 #clock-cells = <1>;
161 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
164 clock-output-names = "pwm0_lpcg_ipg_clk",
169 power-domains = <&pd IMX_SC_R_PWM_0>;
172 pwm1_lpcg: clock-controller@5d410000 {
173 compatible = "fsl,imx8qxp-lpcg";
175 #clock-cells = <1>;
181 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
184 clock-output-names = "pwm1_lpcg_ipg_clk",
189 power-domains = <&pd IMX_SC_R_PWM_1>;
192 pwm2_lpcg: clock-controller@5d420000 {
193 compatible = "fsl,imx8qxp-lpcg";
195 #clock-cells = <1>;
201 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
204 clock-output-names = "pwm2_lpcg_ipg_clk",
209 power-domains = <&pd IMX_SC_R_PWM_2>;
212 pwm3_lpcg: clock-controller@5d430000 {
213 compatible = "fsl,imx8qxp-lpcg";
215 #clock-cells = <1>;
221 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
224 clock-output-names = "pwm3_lpcg_ipg_clk",
229 power-domains = <&pd IMX_SC_R_PWM_3>;
232 pwm4_lpcg: clock-controller@5d440000 {
233 compatible = "fsl,imx8qxp-lpcg";
235 #clock-cells = <1>;
241 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
244 clock-output-names = "pwm4_lpcg_ipg_clk",
249 power-domains = <&pd IMX_SC_R_PWM_4>;
252 pwm5_lpcg: clock-controller@5d450000 {
253 compatible = "fsl,imx8qxp-lpcg";
255 #clock-cells = <1>;
261 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
264 clock-output-names = "pwm5_lpcg_ipg_clk",
269 power-domains = <&pd IMX_SC_R_PWM_5>;
272 pwm6_lpcg: clock-controller@5d460000 {
273 compatible = "fsl,imx8qxp-lpcg";
275 #clock-cells = <1>;
281 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
284 clock-output-names = "pwm6_lpcg_ipg_clk",
289 power-domains = <&pd IMX_SC_R_PWM_6>;
292 pwm7_lpcg: clock-controller@5d470000 {
293 compatible = "fsl,imx8qxp-lpcg";
295 #clock-cells = <1>;
301 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
304 clock-output-names = "pwm7_lpcg_ipg_clk",
309 power-domains = <&pd IMX_SC_R_PWM_7>;