Lines Matching +full:clock +full:- +full:controller
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: MediaTek Functional Clock Controller for MT8192
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
13 The Mediatek functional clock controller provides various clocks on MT8192.
18 - enum:
19 - mediatek,mt8192-scp_adsp
20 - mediatek,mt8192-imp_iic_wrap_c
21 - mediatek,mt8192-imp_iic_wrap_e
22 - mediatek,mt8192-imp_iic_wrap_s
23 - mediatek,mt8192-imp_iic_wrap_ws
24 - mediatek,mt8192-imp_iic_wrap_w
25 - mediatek,mt8192-imp_iic_wrap_n
26 - mediatek,mt8192-msdc_top
27 - mediatek,mt8192-msdc
28 - mediatek,mt8192-mfgcfg
29 - mediatek,mt8192-imgsys
30 - mediatek,mt8192-imgsys2
31 - mediatek,mt8192-vdecsys_soc
32 - mediatek,mt8192-vdecsys
33 - mediatek,mt8192-vencsys
34 - mediatek,mt8192-camsys
35 - mediatek,mt8192-camsys_rawa
36 - mediatek,mt8192-camsys_rawb
37 - mediatek,mt8192-camsys_rawc
38 - mediatek,mt8192-ipesys
39 - mediatek,mt8192-mdpsys
44 '#clock-cells':
48 - compatible
49 - reg
54 - |
55 scp_adsp: clock-controller@10720000 {
56 compatible = "mediatek,mt8192-scp_adsp";
58 #clock-cells = <1>;
61 - |
62 imp_iic_wrap_c: clock-controller@11007000 {
63 compatible = "mediatek,mt8192-imp_iic_wrap_c";
65 #clock-cells = <1>;
68 - |
69 imp_iic_wrap_e: clock-controller@11cb1000 {
70 compatible = "mediatek,mt8192-imp_iic_wrap_e";
72 #clock-cells = <1>;
75 - |
76 imp_iic_wrap_s: clock-controller@11d03000 {
77 compatible = "mediatek,mt8192-imp_iic_wrap_s";
79 #clock-cells = <1>;
82 - |
83 imp_iic_wrap_ws: clock-controller@11d23000 {
84 compatible = "mediatek,mt8192-imp_iic_wrap_ws";
86 #clock-cells = <1>;
89 - |
90 imp_iic_wrap_w: clock-controller@11e01000 {
91 compatible = "mediatek,mt8192-imp_iic_wrap_w";
93 #clock-cells = <1>;
96 - |
97 imp_iic_wrap_n: clock-controller@11f02000 {
98 compatible = "mediatek,mt8192-imp_iic_wrap_n";
100 #clock-cells = <1>;
103 - |
104 msdc_top: clock-controller@11f10000 {
105 compatible = "mediatek,mt8192-msdc_top";
107 #clock-cells = <1>;
110 - |
111 msdc: clock-controller@11f60000 {
112 compatible = "mediatek,mt8192-msdc";
114 #clock-cells = <1>;
117 - |
118 mfgcfg: clock-controller@13fbf000 {
119 compatible = "mediatek,mt8192-mfgcfg";
121 #clock-cells = <1>;
124 - |
125 imgsys: clock-controller@15020000 {
126 compatible = "mediatek,mt8192-imgsys";
128 #clock-cells = <1>;
131 - |
132 imgsys2: clock-controller@15820000 {
133 compatible = "mediatek,mt8192-imgsys2";
135 #clock-cells = <1>;
138 - |
139 vdecsys_soc: clock-controller@1600f000 {
140 compatible = "mediatek,mt8192-vdecsys_soc";
142 #clock-cells = <1>;
145 - |
146 vdecsys: clock-controller@1602f000 {
147 compatible = "mediatek,mt8192-vdecsys";
149 #clock-cells = <1>;
152 - |
153 vencsys: clock-controller@17000000 {
154 compatible = "mediatek,mt8192-vencsys";
156 #clock-cells = <1>;
159 - |
160 camsys: clock-controller@1a000000 {
161 compatible = "mediatek,mt8192-camsys";
163 #clock-cells = <1>;
166 - |
167 camsys_rawa: clock-controller@1a04f000 {
168 compatible = "mediatek,mt8192-camsys_rawa";
170 #clock-cells = <1>;
173 - |
174 camsys_rawb: clock-controller@1a06f000 {
175 compatible = "mediatek,mt8192-camsys_rawb";
177 #clock-cells = <1>;
180 - |
181 camsys_rawc: clock-controller@1a08f000 {
182 compatible = "mediatek,mt8192-camsys_rawc";
184 #clock-cells = <1>;
187 - |
188 ipesys: clock-controller@1b000000 {
189 compatible = "mediatek,mt8192-ipesys";
191 #clock-cells = <1>;
194 - |
195 mdpsys: clock-controller@1f000000 {
196 compatible = "mediatek,mt8192-mdpsys";
198 #clock-cells = <1>;