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/Linux-v6.1/drivers/clk/hisilicon/
Dclk.c51 clk_data->clk_data.clks = clk_table; in hisi_clk_alloc()
80 clk_data->clk_data.clks = clk_table; in hisi_clk_init()
91 int hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *clks, in hisi_clk_register_fixed_rate() argument
98 clk = clk_register_fixed_rate(NULL, clks[i].name, in hisi_clk_register_fixed_rate()
99 clks[i].parent_name, in hisi_clk_register_fixed_rate()
100 clks[i].flags, in hisi_clk_register_fixed_rate()
101 clks[i].fixed_rate); in hisi_clk_register_fixed_rate()
104 __func__, clks[i].name); in hisi_clk_register_fixed_rate()
107 data->clk_data.clks[clks[i].id] = clk; in hisi_clk_register_fixed_rate()
114 clk_unregister_fixed_rate(data->clk_data.clks[clks[i].id]); in hisi_clk_register_fixed_rate()
[all …]
/Linux-v6.1/drivers/clk/mmp/
Dclk.c21 unit->clk_data.clks = clk_table; in mmp_clk_init()
27 struct mmp_param_fixed_rate_clk *clks, in mmp_register_fixed_rate_clks() argument
34 clk = clk_register_fixed_rate(NULL, clks[i].name, in mmp_register_fixed_rate_clks()
35 clks[i].parent_name, in mmp_register_fixed_rate_clks()
36 clks[i].flags, in mmp_register_fixed_rate_clks()
37 clks[i].fixed_rate); in mmp_register_fixed_rate_clks()
40 __func__, clks[i].name); in mmp_register_fixed_rate_clks()
43 if (clks[i].id) in mmp_register_fixed_rate_clks()
44 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_rate_clks()
49 struct mmp_param_fixed_factor_clk *clks, in mmp_register_fixed_factor_clks() argument
[all …]
/Linux-v6.1/drivers/clk/imx/
Dclk-imx8ulp.c149 struct clk_hw **clks; in imx8ulp_clk_cgc1_init() local
158 clks = clk_data->hws; in imx8ulp_clk_cgc1_init()
160 clks[IMX8ULP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8ulp_clk_cgc1_init()
167 …clks[IMX8ULP_CLK_SPLL2_PRE_SEL] = imx_clk_hw_mux_flags("spll2_pre_sel", base + 0x510, 0, 1, pll_pr… in imx8ulp_clk_cgc1_init()
168 …clks[IMX8ULP_CLK_SPLL3_PRE_SEL] = imx_clk_hw_mux_flags("spll3_pre_sel", base + 0x610, 0, 1, pll_pr… in imx8ulp_clk_cgc1_init()
170 …clks[IMX8ULP_CLK_SPLL2] = imx_clk_hw_pllv4(IMX_PLLV4_IMX8ULP, "spll2", "spll2_pre_sel", base + 0x5… in imx8ulp_clk_cgc1_init()
171 …clks[IMX8ULP_CLK_SPLL3] = imx_clk_hw_pllv4(IMX_PLLV4_IMX8ULP, "spll3", "spll3_pre_sel", base + 0x6… in imx8ulp_clk_cgc1_init()
172 clks[IMX8ULP_CLK_SPLL3_VCODIV] = imx_clk_hw_divider("spll3_vcodiv", "spll3", base + 0x604, 0, 6); in imx8ulp_clk_cgc1_init()
174 …clks[IMX8ULP_CLK_SPLL3_PFD0] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX8ULP, "spll3_pfd0", "spll3_vcodiv", b… in imx8ulp_clk_cgc1_init()
175 …clks[IMX8ULP_CLK_SPLL3_PFD1] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX8ULP, "spll3_pfd1", "spll3_vcodiv", b… in imx8ulp_clk_cgc1_init()
[all …]
/Linux-v6.1/drivers/clk/
Dclk-bulk.c16 struct clk_bulk_data *clks) in of_clk_bulk_get() argument
22 clks[i].id = NULL; in of_clk_bulk_get()
23 clks[i].clk = NULL; in of_clk_bulk_get()
27 of_property_read_string_index(np, "clock-names", i, &clks[i].id); in of_clk_bulk_get()
28 clks[i].clk = of_clk_get(np, i); in of_clk_bulk_get()
29 if (IS_ERR(clks[i].clk)) { in of_clk_bulk_get()
30 ret = PTR_ERR(clks[i].clk); in of_clk_bulk_get()
33 clks[i].clk = NULL; in of_clk_bulk_get()
41 clk_bulk_put(i, clks); in of_clk_bulk_get()
47 struct clk_bulk_data **clks) in of_clk_bulk_get_all() argument
[all …]
/Linux-v6.1/drivers/clk/mxs/
Dclk-imx28.c145 static struct clk *clks[clk_max]; variable
167 clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); in mx28_clocks_init()
168 clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); in mx28_clocks_init()
169 clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000); in mx28_clocks_init()
170 clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000); in mx28_clocks_init()
171 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0); in mx28_clocks_init()
172 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1); in mx28_clocks_init()
173 clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2); in mx28_clocks_init()
174 clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3); in mx28_clocks_init()
175 clks[ref_pix] = mxs_clk_ref("ref_pix", "pll0", FRAC1, 0); in mx28_clocks_init()
[all …]
Dclk-imx23.c90 static struct clk *clks[clk_max]; variable
112 clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); in mx23_clocks_init()
113 clks[pll] = mxs_clk_pll("pll", "ref_xtal", PLLCTRL0, 16, 480000000); in mx23_clocks_init()
114 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll", FRAC, 0); in mx23_clocks_init()
115 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll", FRAC, 1); in mx23_clocks_init()
116 clks[ref_pix] = mxs_clk_ref("ref_pix", "pll", FRAC, 2); in mx23_clocks_init()
117 clks[ref_io] = mxs_clk_ref("ref_io", "pll", FRAC, 3); in mx23_clocks_init()
118 clks[saif_sel] = mxs_clk_mux("saif_sel", CLKSEQ, 0, 1, sel_pll, ARRAY_SIZE(sel_pll)); in mx23_clocks_init()
119 clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 1, 1, sel_pix, ARRAY_SIZE(sel_pix)); in mx23_clocks_init()
120 clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 4, 1, sel_io, ARRAY_SIZE(sel_io)); in mx23_clocks_init()
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dimx6sx.dtsi84 clocks = <&clks IMX6SX_CLK_ARM>,
85 <&clks IMX6SX_CLK_PLL2_PFD2>,
86 <&clks IMX6SX_CLK_STEP>,
87 <&clks IMX6SX_CLK_PLL1_SW>,
88 <&clks IMX6SX_CLK_PLL1_SYS>;
170 clocks = <&clks IMX6SX_CLK_OCRAM_S>;
179 clocks = <&clks IMX6SX_CLK_OCRAM>;
205 clocks = <&clks IMX6SX_CLK_GPU>,
206 <&clks IMX6SX_CLK_GPU>,
207 <&clks IMX6SX_CLK_GPU>;
[all …]
Dimx27.dtsi72 clocks = <&clks IMX27_CLK_CPU_DIV>;
95 clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
96 <&clks IMX27_CLK_DMA_AHB_GATE>;
106 clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
113 clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
114 <&clks IMX27_CLK_PER1_GATE>;
122 clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
123 <&clks IMX27_CLK_PER1_GATE>;
131 clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
132 <&clks IMX27_CLK_PER1_GATE>;
[all …]
Dimx6ul.dtsi79 clocks = <&clks IMX6UL_CLK_ARM>,
80 <&clks IMX6UL_CLK_PLL2_BUS>,
81 <&clks IMX6UL_CLK_PLL2_PFD2>,
82 <&clks IMX6UL_CA7_SECONDARY_SEL>,
83 <&clks IMX6UL_CLK_STEP>,
84 <&clks IMX6UL_CLK_PLL1_SW>,
85 <&clks IMX6UL_CLK_PLL1_SYS>;
177 clocks = <&clks IMX6UL_CLK_APBHDMA>;
188 clocks = <&clks IMX6UL_CLK_GPMI_IO>,
189 <&clks IMX6UL_CLK_GPMI_APB>,
[all …]
Dimx6qdl.dtsi163 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
172 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
173 <&clks IMX6QDL_CLK_GPMI_APB>,
174 <&clks IMX6QDL_CLK_GPMI_BCH>,
175 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
176 <&clks IMX6QDL_CLK_PER1_BCH>;
188 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
189 <&clks IMX6QDL_CLK_HDMI_ISFR>;
219 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
220 <&clks IMX6QDL_CLK_GPU3D_CORE>,
[all …]
Dvfxxx.dtsi93 clocks = <&clks VF610_CLK_DMAMUX0>,
94 <&clks VF610_CLK_DMAMUX1>;
102 clocks = <&clks VF610_CLK_FLEXCAN0>,
103 <&clks VF610_CLK_FLEXCAN0>;
112 clocks = <&clks VF610_CLK_UART0>;
124 clocks = <&clks VF610_CLK_UART1>;
136 clocks = <&clks VF610_CLK_UART2>;
148 clocks = <&clks VF610_CLK_UART3>;
162 clocks = <&clks VF610_CLK_DSPI0>;
177 clocks = <&clks VF610_CLK_DSPI1>;
[all …]
Dimx53.dtsi56 clocks = <&clks IMX5_CLK_ARM>;
121 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
129 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
146 clocks = <&clks IMX5_CLK_SATA_GATE>,
147 <&clks IMX5_CLK_SATA_REF>,
148 <&clks IMX5_CLK_AHB>;
159 clocks = <&clks IMX5_CLK_IPU_GATE>,
160 <&clks IMX5_CLK_IPU_DI0_GATE>,
161 <&clks IMX5_CLK_IPU_DI1_GATE>;
221 clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
[all …]
Dimx25.dtsi95 clocks = <&clks 48>;
106 clocks = <&clks 48>;
116 clocks = <&clks 75>, <&clks 75>;
125 clocks = <&clks 76>, <&clks 76>;
134 clocks = <&clks 120>, <&clks 57>;
143 clocks = <&clks 121>, <&clks 57>;
153 clocks = <&clks 48>;
163 clocks = <&clks 51>;
174 clocks = <&clks 78>, <&clks 78>;
185 clocks = <&clks 102>;
[all …]
Dimx51.dtsi83 clocks = <&clks IMX5_CLK_CPU_PODF>;
102 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
135 clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
145 clocks = <&clks IMX5_CLK_IPU_GATE>,
146 <&clks IMX5_CLK_IPU_DI0_GATE>,
147 <&clks IMX5_CLK_IPU_DI1_GATE>;
192 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
193 <&clks IMX5_CLK_DUMMY>,
194 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
203 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
[all …]
Dimx7s.dtsi77 clocks = <&clks IMX7D_CLK_ARM>;
114 clocks = <&clks IMX7D_USB_PHY1_CLK>;
121 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
189 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
216 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
231 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
266 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
289 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
304 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
423 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
[all …]
Dimx6sll.dtsi68 clocks = <&clks IMX6SLL_CLK_ARM>,
69 <&clks IMX6SLL_CLK_PLL2_PFD2>,
70 <&clks IMX6SLL_CLK_STEP>,
71 <&clks IMX6SLL_CLK_PLL1_SW>,
72 <&clks IMX6SLL_CLK_PLL1_SYS>;
162 clocks = <&clks IMX6SLL_CLK_SPDIF_GCLK>,
163 <&clks IMX6SLL_CLK_OSC>,
164 <&clks IMX6SLL_CLK_SPDIF>,
165 <&clks IMX6SLL_CLK_DUMMY>,
166 <&clks IMX6SLL_CLK_DUMMY>,
[all …]
Dimx35.dtsi81 clocks = <&clks 51>;
92 clocks = <&clks 53>;
101 clocks = <&clks 9>, <&clks 70>;
110 clocks = <&clks 9>, <&clks 71>;
121 clocks = <&clks 52>;
132 clocks = <&clks 68>;
145 clocks = <&clks 35 &clks 35>;
155 clocks = <&clks 56>;
175 clocks = <&clks 9>, <&clks 72>;
187 clocks = <&clks 36 &clks 36>;
[all …]
Dimx50.dtsi91 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
122 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
123 <&clks IMX5_CLK_DUMMY>,
124 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
134 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
135 <&clks IMX5_CLK_DUMMY>,
136 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
146 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
147 <&clks IMX5_CLK_UART3_PER_GATE>;
158 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
[all …]
Dimx6sl.dtsi70 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
71 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
72 <&clks IMX6SL_CLK_PLL1_SYS>;
121 clocks = <&clks IMX6SL_CLK_OCRAM>;
165 clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
166 <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
167 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
168 <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
169 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
184 clocks = <&clks IMX6SL_CLK_ECSPI1>,
[all …]
Dimx31.dtsi77 clocks = <&clks 33>;
87 clocks = <&clks 35>;
97 clocks = <&clks 26>;
105 clocks = <&clks 10>, <&clks 30>;
114 clocks = <&clks 10>, <&clks 31>;
123 clocks = <&clks 34>;
133 clocks = <&clks 10>, <&clks 53>;
146 clocks = <&clks 46>;
153 clocks = <&clks 10>, <&clks 49>;
163 clocks = <&clks 10>, <&clks 50>;
[all …]
/Linux-v6.1/drivers/clk/socfpga/
Dclk-gate-s10.c127 struct clk_hw *s10_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase) in s10_register_gate() argument
132 const char *parent_name = clks->parent_name; in s10_register_gate()
139 socfpga_clk->hw.reg = regbase + clks->gate_reg; in s10_register_gate()
140 socfpga_clk->hw.bit_idx = clks->gate_idx; in s10_register_gate()
145 socfpga_clk->fixed_div = clks->fixed_div; in s10_register_gate()
147 if (clks->div_reg) in s10_register_gate()
148 socfpga_clk->div_reg = regbase + clks->div_reg; in s10_register_gate()
152 socfpga_clk->width = clks->div_width; in s10_register_gate()
153 socfpga_clk->shift = clks->div_offset; in s10_register_gate()
155 if (clks->bypass_reg) in s10_register_gate()
[all …]
Dclk-periph-s10.c101 struct clk_hw *s10_register_periph(const struct stratix10_perip_c_clock *clks, in s10_register_periph() argument
107 const char *name = clks->name; in s10_register_periph()
108 const char *parent_name = clks->parent_name; in s10_register_periph()
115 periph_clk->hw.reg = reg + clks->offset; in s10_register_periph()
119 init.flags = clks->flags; in s10_register_periph()
121 init.num_parents = clks->num_parents; in s10_register_periph()
124 init.parent_data = clks->parent_data; in s10_register_periph()
137 struct clk_hw *n5x_register_periph(const struct n5x_perip_c_clock *clks, in n5x_register_periph() argument
143 const char *name = clks->name; in n5x_register_periph()
144 const char *parent_name = clks->parent_name; in n5x_register_periph()
[all …]
/Linux-v6.1/arch/powerpc/boot/dts/
Dmpc5121.dtsi50 clocks = <&clks MPC512x_CLK_MBX_BUS>,
51 <&clks MPC512x_CLK_MBX_3D>,
52 <&clks MPC512x_CLK_MBX>;
67 clocks = <&clks MPC512x_CLK_NFC>;
134 clks: clock@f00 { label
159 clocks = <&clks MPC512x_CLK_BDLC>,
160 <&clks MPC512x_CLK_IPS>,
161 <&clks MPC512x_CLK_SYS>,
162 <&clks MPC512x_CLK_REF>,
163 <&clks MPC512x_CLK_MSCAN0_MCLK>;
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
Ddcn20_clk_mgr.c109 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; in dcn20_update_clocks_update_dpp_dto()
136 if (clk_mgr->base.clks.dppclk_khz == 0 || clk_mgr->base.clks.dispclk_khz == 0) in dcn20_update_clocks_update_dentist()
140 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz; in dcn20_update_clocks_update_dentist()
142 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz; in dcn20_update_clocks_update_dentist()
237 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn2_update_clocks()
262 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn2_update_clocks()
263 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn2_update_clocks()
265 …pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz… in dcn2_update_clocks()
269 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { in dcn2_update_clocks()
270 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in dcn2_update_clocks()
[all …]
/Linux-v6.1/drivers/clk/axis/
Dclk-artpec6.c43 struct clk **clks; in of_artpec6_clkctrl_setup() local
56 clks = clkdata->clk_table; in of_artpec6_clkctrl_setup()
59 clks[i] = ERR_PTR(-EPROBE_DEFER); in of_artpec6_clkctrl_setup()
85 clks[ARTPEC6_CLK_CPU] = in of_artpec6_clkctrl_setup()
88 clks[ARTPEC6_CLK_CPU_PERIPH] = in of_artpec6_clkctrl_setup()
92 clks[ARTPEC6_CLK_UART_PCLK] = in of_artpec6_clkctrl_setup()
94 clks[ARTPEC6_CLK_UART_REFCLK] = in of_artpec6_clkctrl_setup()
98 clks[ARTPEC6_CLK_SPI_PCLK] = in of_artpec6_clkctrl_setup()
100 clks[ARTPEC6_CLK_SPI_SSPCLK] = in of_artpec6_clkctrl_setup()
104 clks[ARTPEC6_CLK_DBG_PCLK] = in of_artpec6_clkctrl_setup()
[all …]

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