Lines Matching full:clks
83 clocks = <&clks IMX5_CLK_CPU_PODF>;
102 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
135 clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
145 clocks = <&clks IMX5_CLK_IPU_GATE>,
146 <&clks IMX5_CLK_IPU_DI0_GATE>,
147 <&clks IMX5_CLK_IPU_DI1_GATE>;
192 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
193 <&clks IMX5_CLK_DUMMY>,
194 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
203 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
204 <&clks IMX5_CLK_DUMMY>,
205 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
215 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
216 <&clks IMX5_CLK_UART3_PER_GATE>;
229 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
230 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
240 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
241 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
254 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
255 <&clks IMX5_CLK_DUMMY>,
256 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
266 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
267 <&clks IMX5_CLK_DUMMY>,
268 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
284 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
294 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
304 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
314 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
324 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
371 clocks = <&clks IMX5_CLK_DUMMY>;
379 clocks = <&clks IMX5_CLK_DUMMY>;
386 clocks = <&clks IMX5_CLK_DUMMY>;
394 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
395 <&clks IMX5_CLK_GPT_HF_GATE>;
408 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
409 <&clks IMX5_CLK_PWM1_HF_GATE>;
418 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
419 <&clks IMX5_CLK_PWM2_HF_GATE>;
428 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
429 <&clks IMX5_CLK_UART1_PER_GATE>;
440 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
441 <&clks IMX5_CLK_UART2_PER_GATE>;
455 clks: ccm@73fd4000{ label
479 clocks = <&clks IMX5_CLK_IIM_GATE>;
491 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
501 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
502 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
511 clocks = <&clks IMX5_CLK_SDMA_GATE>,
512 <&clks IMX5_CLK_AHB>;
524 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
525 <&clks IMX5_CLK_CSPI_IPG_GATE>;
536 clocks = <&clks IMX5_CLK_I2C2_GATE>;
546 clocks = <&clks IMX5_CLK_I2C1_GATE>;
555 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
556 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
568 clocks = <&clks IMX5_CLK_DUMMY>;
583 clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
601 clocks = <&clks IMX5_CLK_NFC_GATE>;
609 clocks = <&clks IMX5_CLK_PATA_GATE>;
618 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
619 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
632 clocks = <&clks IMX5_CLK_FEC_GATE>,
633 <&clks IMX5_CLK_FEC_GATE>,
634 <&clks IMX5_CLK_FEC_GATE>;
643 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
644 <&clks IMX5_CLK_VPU_GATE>;
654 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
655 <&clks IMX5_CLK_SAHARA_IPG_GATE>;