Lines Matching full:clks
77 clocks = <&clks IMX7D_CLK_ARM>;
114 clocks = <&clks IMX7D_USB_PHY1_CLK>;
121 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
189 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
216 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
231 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
266 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
289 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
304 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
423 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
430 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
438 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
446 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
460 clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
461 <&clks IMX7D_GPT1_ROOT_CLK>;
469 clocks = <&clks IMX7D_GPT2_ROOT_CLK>,
470 <&clks IMX7D_GPT2_ROOT_CLK>;
479 clocks = <&clks IMX7D_GPT3_ROOT_CLK>,
480 <&clks IMX7D_GPT3_ROOT_CLK>;
489 clocks = <&clks IMX7D_GPT4_ROOT_CLK>,
490 <&clks IMX7D_GPT4_ROOT_CLK>;
499 clocks = <&clks IMX7D_KPP_ROOT_CLK>;
554 clocks = <&clks IMX7D_OCOTP_CLK>;
607 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
621 clocks = <&clks IMX7D_SNVS_CLK>;
629 clocks = <&clks IMX7D_SNVS_CLK>;
637 clks: clock-controller@30380000 { label
699 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
709 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
721 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
722 <&clks IMX7D_ECSPI4_ROOT_CLK>;
734 clocks = <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
735 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
736 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
737 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>;
748 clocks = <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
749 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
750 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
751 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>;
759 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
760 <&clks IMX7D_PWM1_ROOT_CLK>;
770 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
771 <&clks IMX7D_PWM2_ROOT_CLK>;
781 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
782 <&clks IMX7D_PWM3_ROOT_CLK>;
792 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
793 <&clks IMX7D_PWM4_ROOT_CLK>;
803 clocks = <&clks IMX7D_CLK_DUMMY>,
804 <&clks IMX7D_CSI_MCLK_ROOT_CLK>,
805 <&clks IMX7D_CLK_DUMMY>;
820 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
821 <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
830 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
831 <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
832 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
878 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
879 <&clks IMX7D_ECSPI1_ROOT_CLK>;
890 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
891 <&clks IMX7D_ECSPI2_ROOT_CLK>;
902 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
903 <&clks IMX7D_ECSPI3_ROOT_CLK>;
913 clocks = <&clks IMX7D_UART1_ROOT_CLK>,
914 <&clks IMX7D_UART1_ROOT_CLK>;
924 clocks = <&clks IMX7D_UART2_ROOT_CLK>,
925 <&clks IMX7D_UART2_ROOT_CLK>;
935 clocks = <&clks IMX7D_UART3_ROOT_CLK>,
936 <&clks IMX7D_UART3_ROOT_CLK>;
946 clocks = <&clks IMX7D_SAI1_IPG_CLK>,
947 <&clks IMX7D_SAI1_ROOT_CLK>,
948 <&clks IMX7D_CLK_DUMMY>,
949 <&clks IMX7D_CLK_DUMMY>;
961 clocks = <&clks IMX7D_SAI2_IPG_CLK>,
962 <&clks IMX7D_SAI2_ROOT_CLK>,
963 <&clks IMX7D_CLK_DUMMY>,
964 <&clks IMX7D_CLK_DUMMY>;
976 clocks = <&clks IMX7D_SAI3_IPG_CLK>,
977 <&clks IMX7D_SAI3_ROOT_CLK>,
978 <&clks IMX7D_CLK_DUMMY>,
979 <&clks IMX7D_CLK_DUMMY>;
994 clocks = <&clks IMX7D_CAAM_CLK>,
995 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
1021 clocks = <&clks IMX7D_CLK_DUMMY>,
1022 <&clks IMX7D_CAN1_ROOT_CLK>;
1032 clocks = <&clks IMX7D_CLK_DUMMY>,
1033 <&clks IMX7D_CAN2_ROOT_CLK>;
1045 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
1055 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
1065 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
1075 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
1084 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
1085 <&clks IMX7D_UART4_ROOT_CLK>;
1095 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
1096 <&clks IMX7D_UART5_ROOT_CLK>;
1106 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
1107 <&clks IMX7D_UART6_ROOT_CLK>;
1117 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
1118 <&clks IMX7D_UART7_ROOT_CLK>;
1127 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1136 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1146 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1157 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1182 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1183 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1184 <&clks IMX7D_USDHC1_ROOT_CLK>;
1194 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1195 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1196 <&clks IMX7D_USDHC2_ROOT_CLK>;
1206 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1207 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1208 <&clks IMX7D_USDHC3_ROOT_CLK>;
1221 clocks = <&clks IMX7D_QSPI_ROOT_CLK>,
1222 <&clks IMX7D_QSPI_ROOT_CLK>;
1231 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1232 <&clks IMX7D_SDMA_CORE_CLK>;
1246 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
1247 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1248 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
1249 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
1250 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
1270 clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1281 clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
1282 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1287 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
1288 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;