| /Linux-v6.1/tools/perf/pmu-events/arch/arm64/ |
| D | recommended.json | 3 "PublicDescription": "Attributable Level 1 data cache access, read",
6 "BriefDescription": "L1D cache access, read"
9 "PublicDescription": "Attributable Level 1 data cache access, write",
12 "BriefDescription": "L1D cache access, write"
15 "PublicDescription": "Attributable Level 1 data cache refill, read",
18 "BriefDescription": "L1D cache refill, read"
21 "PublicDescription": "Attributable Level 1 data cache refill, write",
24 "BriefDescription": "L1D cache refill, write"
27 "PublicDescription": "Attributable Level 1 data cache refill, inner",
30 "BriefDescription": "L1D cache refill, inner"
[all …]
|
| D | common-and-microarch.json | 9 "PublicDescription": "Level 1 instruction cache refill",
12 "BriefDescription": "Level 1 instruction cache refill"
21 "PublicDescription": "Level 1 data cache refill",
24 "BriefDescription": "Level 1 data cache refill"
27 "PublicDescription": "Level 1 data cache access",
30 "BriefDescription": "Level 1 data cache access"
123 "PublicDescription": "Attributable Level 1 instruction cache access",
126 "BriefDescription": "Attributable Level 1 instruction cache access"
129 "PublicDescription": "Attributable Level 1 data cache write-back",
132 "BriefDescription": "Attributable Level 1 data cache write-back"
[all …]
|
| /Linux-v6.1/Documentation/devicetree/bindings/arm/socionext/ |
| D | socionext,uniphier-system-cache.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier outer cache controller
10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
11 controller system. All of them have a level 2 cache controller, and some
12 have a level 3 cache controller as well.
15 - Masahiro Yamada <yamada.masahiro@socionext.com>
19 const: socionext,uniphier-system-cache
[all …]
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| /Linux-v6.1/tools/perf/pmu-events/arch/s390/cf_z10/ |
| D | basic.json | 3 "Unit": "CPU-M-CF",
10 "Unit": "CPU-M-CF",
17 "Unit": "CPU-M-CF",
20 "BriefDescription": "Level-1 I-Cache Directory Write Count",
21 …scription": "This counter counts the total number of level-1 instruction-cache or unified-cache di…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
28 …: "This counter counts the total number of cache penalty cycles for level-1 instruction cache or u…
31 "Unit": "CPU-M-CF",
34 "BriefDescription": "Level-1 D-Cache Directory Write Count",
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/s390/cf_z13/ |
| D | basic.json | 3 "Unit": "CPU-M-CF",
10 "Unit": "CPU-M-CF",
17 "Unit": "CPU-M-CF",
20 "BriefDescription": "Level-1 I-Cache Directory Write Count",
21 …scription": "This counter counts the total number of level-1 instruction-cache or unified-cache di…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
28 …: "This counter counts the total number of cache penalty cycles for level-1 instruction cache or u…
31 "Unit": "CPU-M-CF",
34 "BriefDescription": "Level-1 D-Cache Directory Write Count",
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/s390/cf_z196/ |
| D | basic.json | 3 "Unit": "CPU-M-CF",
10 "Unit": "CPU-M-CF",
17 "Unit": "CPU-M-CF",
20 "BriefDescription": "Level-1 I-Cache Directory Write Count",
21 …scription": "This counter counts the total number of level-1 instruction-cache or unified-cache di…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
28 …: "This counter counts the total number of cache penalty cycles for level-1 instruction cache or u…
31 "Unit": "CPU-M-CF",
34 "BriefDescription": "Level-1 D-Cache Directory Write Count",
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/s390/cf_zec12/ |
| D | basic.json | 3 "Unit": "CPU-M-CF",
10 "Unit": "CPU-M-CF",
17 "Unit": "CPU-M-CF",
20 "BriefDescription": "Level-1 I-Cache Directory Write Count",
21 …scription": "This counter counts the total number of level-1 instruction-cache or unified-cache di…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
28 …: "This counter counts the total number of cache penalty cycles for level-1 instruction cache or u…
31 "Unit": "CPU-M-CF",
34 "BriefDescription": "Level-1 D-Cache Directory Write Count",
[all …]
|
| /Linux-v6.1/arch/arm64/boot/dts/amd/ |
| D | amd-seattle-cpus.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 #address-cells = <0x1>;
6 #size-cells = <0x0>;
8 cpu-map {
45 compatible = "arm,cortex-a57";
47 enable-method = "psci";
49 i-cache-size = <0xC000>;
50 i-cache-line-size = <64>;
51 i-cache-sets = <256>;
52 d-cache-size = <0x8000>;
[all …]
|
| /Linux-v6.1/arch/m68k/include/asm/ |
| D | m53xxacr.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m53xxacr.h -- ColdFire version 3 core cache support
17 * cache setup. They have a unified instruction and data cache, with
18 * configurable write-through or copy-back operation.
22 * Define the Cache Control register flags.
24 #define CACR_EC 0x80000000 /* Enable cache */
27 #define CACR_HLCK 0x08000000 /* Half cache lock mode */
28 #define CACR_CINVA 0x01000000 /* Invalidate cache */
30 #define CACR_DCM_WT 0x00000000 /* Cacheable write-through */
31 #define CACR_DCM_CB 0x00000100 /* Cacheable copy-back */
[all …]
|
| /Linux-v6.1/Documentation/devicetree/bindings/riscv/ |
| D | sifive,ccache0.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Composable Cache Controller
11 - Sagar Kadam <sagar.kadam@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
15 The SiFive Composable Cache Controller is used to provide access to fast copies
16 of memory for masters in a Core Complex. The Composable Cache Controller also
17 acts as directory-based coherency manager.
25 - sifive,ccache0
[all …]
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| /Linux-v6.1/arch/arm/mm/ |
| D | cache-v6.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v6.S
15 #include "proc-macros.S"
25 * Flush the whole I-cache.
27 * ARM1136 erratum 411920 - Invalidate Instruction Cache operation can fail.
32 * r0 - set to 0
33 * r1 - corrupted
40 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
41 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
42 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
[all …]
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| D | cache-uniphier.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2015-2016 Socionext Inc.
15 #include <asm/hardware/cache-uniphier.h>
21 #define UNIPHIER_SSCC_ACT BIT(19) /* Inst-Data separate */
23 #define UNIPHIER_SSCC_PRD BIT(17) /* enable pre-fetch */
24 #define UNIPHIER_SSCC_ON BIT(0) /* enable cache */
25 #define UNIPHIER_SSCLPDAWCR 0x30 /* Unified/Data Active Way Control */
32 #define UNIPHIER_SSCOPE 0x244 /* Cache Operation Primitive Entry */
37 #define UNIPHIER_SSCOPE_CM_FLUSH_PREFETCH 0x9 /* flush p-fetch buf */
38 #define UNIPHIER_SSCOQM 0x248 /* Cache Operation Queue Mode */
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/ |
| D | cache.json | 3 "PublicDescription": "This event counts any instruction fetch which misses in the cache.",
15 …r store operation or page table walk access which looks up in the L1 data cache. In particular, an…
23 …on cache access or Level 0 Macro-op cache access. This event counts any instruction fetch which ac…
27 …t counts any write-back of data from the L1 data cache to L2 or L3. This counts both victim line e…
31 …from L1 which looks up in the L2 cache, and any write-back from the L1 to the L2. Snoops from outs…
35 …"PublicDescription": "L2 data cache refill. This event counts any cacheable transaction from L1 wh…
39 …"PublicDescription": "This event counts any write-back of data from the L2 cache to outside the co…
43 …ent counts any full cache line write into the L2 cache which does not cause a linefill, including …
57 …ent counts any full cache line write into the L3 cache which does not cause a linefill, including …
64 "BriefDescription": "Attributable Level 3 unified cache refill."
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/s390/cf_z16/ |
| D | basic.json | 3 "Unit": "CPU-M-CF",
10 "Unit": "CPU-M-CF",
17 "Unit": "CPU-M-CF",
20 "BriefDescription": "Level-1 I-Cache Directory Write Count",
21 …scription": "This counter counts the total number of level-1 instruction-cache or unified-cache di…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
28 …: "This counter counts the total number of cache penalty cycles for level-1 instruction cache or u…
31 "Unit": "CPU-M-CF",
34 "BriefDescription": "Level-1 D-Cache Directory Write Count",
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/s390/cf_z14/ |
| D | basic.json | 3 "Unit": "CPU-M-CF",
10 "Unit": "CPU-M-CF",
17 "Unit": "CPU-M-CF",
20 "BriefDescription": "Level-1 I-Cache Directory Write Count",
21 …scription": "This counter counts the total number of level-1 instruction-cache or unified-cache di…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
28 …: "This counter counts the total number of cache penalty cycles for level-1 instruction cache or u…
31 "Unit": "CPU-M-CF",
34 "BriefDescription": "Level-1 D-Cache Directory Write Count",
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/s390/cf_z15/ |
| D | basic.json | 3 "Unit": "CPU-M-CF",
10 "Unit": "CPU-M-CF",
17 "Unit": "CPU-M-CF",
20 "BriefDescription": "Level-1 I-Cache Directory Write Count",
21 …scription": "This counter counts the total number of level-1 instruction-cache or unified-cache di…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
28 …: "This counter counts the total number of cache penalty cycles for level-1 instruction cache or u…
31 "Unit": "CPU-M-CF",
34 "BriefDescription": "Level-1 D-Cache Directory Write Count",
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/ |
| D | cache.json | 111 …"Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetcher which…
114 …"Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetcher which…
117 …cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event …
120 …cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event …
123 …cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which c…
126 …cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which c…
141 … 2 cache write streaming mode. This event counts for each cycle where the core is in write-streami…
144 … 2 cache write streaming mode. This event counts for each cycle where the core is in write-streami…
147 … 3 cache write streaming mode. This event counts for each cycle where the core is in write-streami…
150 … 3 cache write streaming mode. This event counts for each cycle where the core is in write-streami…
[all …]
|
| /Linux-v6.1/Documentation/devicetree/bindings/arm/ |
| D | l2c2x0.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM L2 Cache Controller
10 - Rob Herring <robh@kernel.org>
14 PL220/PL310 and variants) based level 2 cache controller. All these various
15 implementations of the L2 cache controller have compatible programming
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
28 - $ref: /schemas/cache-controller.yaml#
[all …]
|
| /Linux-v6.1/arch/powerpc/kernel/ |
| D | cacheinfo.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Processor cache information made available to userspace via sysfs;
26 /* per-cpu object for tracking:
27 * - a "cache" kobject for the top-level directory
28 * - a list of "index" objects representing the cpu's local cache hierarchy
31 struct kobject *kobj; /* bare (not embedded) kobject for cache
36 /* "index" object: each cpu's cache directory has an index
37 * subdirectory corresponding to a cache object associated with the
43 struct cache *cache; member
47 * cache type */
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/ |
| D | cache.json | 111 "PublicDescription": "Number of ways read in the instruction cache - Tag RAM",
114 "BriefDescription": "Number of ways read in the instruction cache - Tag RAM"
117 "PublicDescription": "Number of ways read in the instruction cache - Data RAM",
120 "BriefDescription": "Number of ways read in the instruction cache - Data RAM"
159 …"PublicDescription": "Prefetch access to unified TLB that caused a page table walk. This event cou…
162 …"BriefDescription": "Prefetch access to unified TLB that caused a page table walk. This event coun…
|
| /Linux-v6.1/arch/arm/boot/dts/ |
| D | vf610.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 next-level-cache = <&L2>;
12 L2: cache-controller@40006000 {
13 compatible = "arm,pl310-cache";
15 cache-unified;
16 cache-level = <2>;
17 arm,data-latency = <3 3 3>;
18 arm,tag-latency = <2 2 2>;
|
| /Linux-v6.1/arch/sh/kernel/cpu/ |
| D | proc.c | 1 // SPDX-License-Identifier: GPL-2.0
21 [CPU_SH4_202] = "SH4-202", [CPU_SH4_501] = "SH4-501",
26 [CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3",
27 [CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723",
36 return cpu_name[c->type]; in get_cpu_subtype()
41 /* Symbolic CPU flags, keep in sync with asm/cpu-features.h */
53 if (!c->flags) { in show_cpuflags()
59 if ((c->flags & (1 << i))) in show_cpuflags()
72 seq_printf(m, "%s size\t: %2dKiB (%d-way)\n", in show_cacheinfo()
82 unsigned int cpu = c - cpu_data; in show_cpuinfo()
[all …]
|
| /Linux-v6.1/drivers/acpi/ |
| D | pptt.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * pptt.c - parsing of Processor Properties Topology Table (PPTT)
8 * which is optionally used to describe the processor and cache topology.
14 * the caches available at that level. Each cache structure optionally
15 * contains properties describing the cache at a given level which can be
33 if (pptt_ref + sizeof(struct acpi_subtable_header) > table_hdr->length) in fetch_pptt_subtable()
38 if (entry->length == 0) in fetch_pptt_subtable()
41 if (pptt_ref + entry->length > table_hdr->length) in fetch_pptt_subtable()
65 if (resource >= node->number_of_priv_resources) in acpi_get_pptt_resource()
81 * acpi_pptt_walk_cache() - Attempt to find the requested acpi_pptt_cache
[all …]
|
| /Linux-v6.1/arch/arm/kernel/ |
| D | head-nommu.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/kernel/head-nommu.S
5 * Copyright (C) 1994-2002 Russell King
6 * Copyright (C) 2003-2006 Hyok S. Choi
8 * Common kernel startup code (non-paged MM)
16 #include <asm/asm-offsets.h>
26 * ---------------------------
29 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
32 * See linux/arch/arm/tools/mach-types for the complete list of machine
47 THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
[all …]
|
| /Linux-v6.1/fs/nilfs2/ |
| D | alloc.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (C) 2006-2008 Nippon Telegraph and Telephone Corporation.
8 * Two allocators were unified by Ryusuke Konishi and Amagai Yoshiji.
19 * nilfs_palloc_entries_per_group - get the number of entries per group
28 return 1UL << (inode->i_blkbits + 3 /* log2(8 = CHAR_BITS) */); in nilfs_palloc_entries_per_group()
40 * nilfs_palloc_req - persistent allocator request and reply
69 * struct nilfs_bh_assoc - block offset and buffer head association
79 * struct nilfs_palloc_cache - persistent object allocator cache
80 * @lock: cache protecting lock
81 * @prev_desc: blockgroup descriptors cache
[all …]
|
