Lines Matching +full:cache +full:- +full:unified
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v6.S
15 #include "proc-macros.S"
25 * Flush the whole I-cache.
27 * ARM1136 erratum 411920 - Invalidate Instruction Cache operation can fail.
32 * r0 - set to 0
33 * r1 - corrupted
40 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
41 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
42 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
49 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
57 * Flush the entire cache.
64 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
66 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
71 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
80 * - mm - mm_struct describing address space
90 * - start - start address (may not be aligned)
91 * - end - end address (exclusive, may not be aligned)
92 * - flags - vm_area_struct flags describing address space
95 * - we have a VIPT cache.
107 * - start - virtual start address of region
108 * - end - virtual end address of region
111 * - the Icache does not read data from the write buffer
123 * - start - virtual start address of region
124 * - end - virtual end address of region
127 * - the Icache does not read data from the write buffer
132 bic r0, r0, #CACHE_LINE_SIZE - 1
143 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
153 * Fault handling for the cache operation above. If the virtual address in r0
154 * isn't mapped, fail with -EFAULT.
157 mov r0, #-EFAULT
169 * - addr - kernel address
170 * - size - region size
174 bic r0, r0, #D_CACHE_LINE_SIZE - 1
179 mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate unified line
194 * Invalidate the data cache within the specified region; we will
196 * purge old data in the cache.
198 * - start - virtual start address of region
199 * - end - virtual end address of region
206 tst r0, #D_CACHE_LINE_SIZE - 1
207 bic r0, r0, #D_CACHE_LINE_SIZE - 1
211 mcrne p15, 0, r0, c7, c11, 1 @ clean unified line
213 tst r1, #D_CACHE_LINE_SIZE - 1
215 ldrbne r2, [r1, #-1] @ read for ownership
216 strbne r2, [r1, #-1] @ write for ownership
218 bic r1, r1, #D_CACHE_LINE_SIZE - 1
222 mcrne p15, 0, r1, c7, c15, 1 @ clean & invalidate unified line
228 mcr p15, 0, r0, c7, c7, 1 @ invalidate unified line
243 * - start - virtual start address of region
244 * - end - virtual end address of region
247 bic r0, r0, #D_CACHE_LINE_SIZE - 1
255 mcr p15, 0, r0, c7, c11, 1 @ clean unified line
266 * - start - virtual start address of region
267 * - end - virtual end address of region
274 bic r0, r0, #D_CACHE_LINE_SIZE - 1
294 * - start - kernel virtual start address
295 * - size - size of region
296 * - dir - DMA direction
313 * - start - kernel virtual start address
314 * - size - size of region
315 * - dir - DMA direction
331 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)