1 // SPDX-License-Identifier: GPL-2.0
21 	[CPU_SH4_202]	= "SH4-202",	[CPU_SH4_501]	= "SH4-501",
26 	[CPU_SH7722]	= "SH7722",	[CPU_SHX3]	= "SH-X3",
27 	[CPU_MXG]	= "MX-G",	[CPU_SH7723]	= "SH7723",
36 	return cpu_name[c->type];  in get_cpu_subtype()
41 /* Symbolic CPU flags, keep in sync with asm/cpu-features.h */
53 	if (!c->flags) {  in show_cpuflags()
59 		if ((c->flags & (1 << i)))  in show_cpuflags()
72 	seq_printf(m, "%s size\t: %2dKiB (%d-way)\n",  in show_cacheinfo()
82 	unsigned int cpu = c - cpu_data;  in show_cpuinfo()
93 	seq_printf(m, "cpu family\t: %s\n", init_utsname()->machine);  in show_cpuinfo()
95 	if (c->cut_major == -1)  in show_cpuinfo()
97 	else if (c->cut_minor == -1)  in show_cpuinfo()
98 		seq_printf(m, "cut\t\t: %d.x\n", c->cut_major);  in show_cpuinfo()
100 		seq_printf(m, "cut\t\t: %d.%d\n", c->cut_major, c->cut_minor);  in show_cpuinfo()
104 	seq_printf(m, "cache type\t: ");  in show_cpuinfo()
107 	 * Check for what type of cache we have, we support both the  in show_cpuinfo()
108 	 * unified cache on the SH-2 and SH-3, as well as the harvard  in show_cpuinfo()
109 	 * style cache on the SH-4.  in show_cpuinfo()
111 	if (c->icache.flags & SH_CACHE_COMBINED) {  in show_cpuinfo()
112 		seq_printf(m, "unified\n");  in show_cpuinfo()
113 		show_cacheinfo(m, "cache", c->icache);  in show_cpuinfo()
116 		show_cacheinfo(m, "icache", c->icache);  in show_cpuinfo()
117 		show_cacheinfo(m, "dcache", c->dcache);  in show_cpuinfo()
120 	/* Optional secondary cache */  in show_cpuinfo()
121 	if (c->flags & CPU_HAS_L2_CACHE)  in show_cpuinfo()
122 		show_cacheinfo(m, "scache", c->scache);  in show_cpuinfo()
124 	seq_printf(m, "address sizes\t: %u bits physical\n", c->phys_bits);  in show_cpuinfo()
127 		     c->loops_per_jiffy/(500000/HZ),  in show_cpuinfo()
128 		     (c->loops_per_jiffy/(5000/HZ)) % 100);  in show_cpuinfo()