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/Linux-v5.15/drivers/gpio/
Dgpio-omap.c77 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
83 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) argument
108 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, in omap_set_gpio_direction() argument
111 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction, in omap_set_gpio_direction()
117 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, in omap_set_gpio_dataout_reg() argument
120 void __iomem *reg = bank->base; in omap_set_gpio_dataout_reg()
124 reg += bank->regs->set_dataout; in omap_set_gpio_dataout_reg()
125 bank->context.dataout |= l; in omap_set_gpio_dataout_reg()
127 reg += bank->regs->clr_dataout; in omap_set_gpio_dataout_reg()
128 bank->context.dataout &= ~l; in omap_set_gpio_dataout_reg()
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Dgpio-rockchip.c73 static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank, in rockchip_gpio_writel() argument
76 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel()
78 if (bank->gpio_type == GPIO_TYPE_V2) in rockchip_gpio_writel()
84 static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank, in rockchip_gpio_readl() argument
87 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_readl()
90 if (bank->gpio_type == GPIO_TYPE_V2) in rockchip_gpio_readl()
98 static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank, in rockchip_gpio_writel_bit() argument
102 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel_bit()
105 if (bank->gpio_type == GPIO_TYPE_V2) { in rockchip_gpio_writel_bit()
120 static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank, in rockchip_gpio_readl_bit() argument
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Dgpio-brcmstb.c36 #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32))) argument
37 #define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN) argument
38 #define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA) argument
39 #define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR) argument
40 #define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC) argument
41 #define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI) argument
42 #define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK) argument
43 #define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL) argument
44 #define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT) argument
76 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_gc_to_priv() local
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/Linux-v5.15/drivers/pinctrl/samsung/
Dpinctrl-exynos.c56 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_mask() local
57 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask()
61 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_mask()
63 mask = readl(bank->eint_base + reg_mask); in exynos_irq_mask()
65 writel(mask, bank->eint_base + reg_mask); in exynos_irq_mask()
67 raw_spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_mask()
74 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_ack() local
75 unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset; in exynos_irq_ack()
77 writel(1 << irqd->hwirq, bank->eint_base + reg_pend); in exynos_irq_ack()
84 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_unmask() local
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Dpinctrl-samsung.c354 * given a pin number that is local to a pin controller, find out the pin bank
355 * and the register base of the pin bank.
359 struct samsung_pin_bank **bank) in pin_to_reg_bank() argument
371 if (bank) in pin_to_reg_bank()
372 *bank = b; in pin_to_reg_bank()
381 struct samsung_pin_bank *bank; in samsung_pinmux_setup() local
393 &reg, &pin_offset, &bank); in samsung_pinmux_setup()
394 type = bank->type; in samsung_pinmux_setup()
403 raw_spin_lock_irqsave(&bank->slock, flags); in samsung_pinmux_setup()
410 raw_spin_unlock_irqrestore(&bank->slock, flags); in samsung_pinmux_setup()
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Dpinctrl-s3c24xx.c96 * @bank: pin bank related to the domain
101 struct samsung_pin_bank *bank; member
134 struct samsung_pin_bank *bank, int pin) in s3c24xx_eint_set_function() argument
136 const struct samsung_pin_bank_type *bank_type = bank->type; in s3c24xx_eint_set_function()
144 reg = d->virt_base + bank->pctl_offset; in s3c24xx_eint_set_function()
148 raw_spin_lock_irqsave(&bank->slock, flags); in s3c24xx_eint_set_function()
152 val |= bank->eint_func << shift; in s3c24xx_eint_set_function()
155 raw_spin_unlock_irqrestore(&bank->slock, flags); in s3c24xx_eint_set_function()
160 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); in s3c24xx_eint_type() local
161 struct samsung_pinctrl_drv_data *d = bank->drvdata; in s3c24xx_eint_type()
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Dpinctrl-s3c64xx.c209 * @bank: pin bank related to the domain
213 struct samsung_pin_bank *bank; member
268 struct samsung_pin_bank *bank, int pin) in s3c64xx_irq_set_function() argument
270 const struct samsung_pin_bank_type *bank_type = bank->type; in s3c64xx_irq_set_function()
278 reg = d->virt_base + bank->pctl_offset; in s3c64xx_irq_set_function()
281 /* 4-bit bank type with 2 con regs */ in s3c64xx_irq_set_function()
289 raw_spin_lock_irqsave(&bank->slock, flags); in s3c64xx_irq_set_function()
293 val |= bank->eint_func << shift; in s3c64xx_irq_set_function()
296 raw_spin_unlock_irqrestore(&bank->slock, flags); in s3c64xx_irq_set_function()
305 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in s3c64xx_gpio_irq_set_mask() local
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Dpinctrl-samsung.h58 * @EINT_TYPE_NONE: bank does not support external interrupts
59 * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
60 * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
61 * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
64 * in a pin bank can support external gpio interrupts or external wakeup
98 * struct samsung_pin_bank_type: pin bank type description
108 * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
109 * @type: type of the bank (register offsets and bitfield widths)
110 * @pctl_offset: starting offset of the pin-bank registers.
111 * @pctl_res_idx: index of base address for pin-bank registers.
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/Linux-v5.15/drivers/pinctrl/renesas/
Dsh_pfc.h461 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \ argument
462 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
463 #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0) argument
465 #define PORT_GP_CFG_2(bank, fn, sfx, cfg) \ argument
466 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
467 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg)
468 #define PORT_GP_2(bank, fn, sfx) PORT_GP_CFG_2(bank, fn, sfx, 0) argument
470 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ argument
471 PORT_GP_CFG_2(bank, fn, sfx, cfg), \
472 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
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/Linux-v5.15/drivers/crypto/qat/qat_common/
Dadf_transport.c37 static int adf_reserve_ring(struct adf_etr_bank_data *bank, u32 ring) in adf_reserve_ring() argument
39 spin_lock(&bank->lock); in adf_reserve_ring()
40 if (bank->ring_mask & (1 << ring)) { in adf_reserve_ring()
41 spin_unlock(&bank->lock); in adf_reserve_ring()
44 bank->ring_mask |= (1 << ring); in adf_reserve_ring()
45 spin_unlock(&bank->lock); in adf_reserve_ring()
49 static void adf_unreserve_ring(struct adf_etr_bank_data *bank, u32 ring) in adf_unreserve_ring() argument
51 spin_lock(&bank->lock); in adf_unreserve_ring()
52 bank->ring_mask &= ~(1 << ring); in adf_unreserve_ring()
53 spin_unlock(&bank->lock); in adf_unreserve_ring()
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Dadf_gen4_hw_data.c11 static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_head() argument
13 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); in read_csr_ring_head()
16 static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_head() argument
19 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); in write_csr_ring_head()
22 static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_tail() argument
24 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); in read_csr_ring_tail()
27 static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_tail() argument
30 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); in write_csr_ring_tail()
33 static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank) in read_csr_e_stat() argument
35 return READ_CSR_E_STAT(csr_base_addr, bank); in read_csr_e_stat()
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Dadf_gen4_hw_data.h27 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
29 ADF_RING_BUNDLE_SIZE * (bank) + \
31 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
33 ADF_RING_BUNDLE_SIZE * (bank) + \
35 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
37 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_E_STAT)
38 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ argument
40 ADF_RING_BUNDLE_SIZE * (bank) + \
42 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ argument
45 u32 _bank = bank; \
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Dadf_transport_debug.c44 struct adf_etr_bank_data *bank = ring->bank; in adf_ring_show() local
45 struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(bank->accel_dev); in adf_ring_show()
46 void __iomem *csr = ring->bank->csr_addr; in adf_ring_show()
51 head = csr_ops->read_csr_ring_head(csr, bank->bank_number, in adf_ring_show()
53 tail = csr_ops->read_csr_ring_tail(csr, bank->bank_number, in adf_ring_show()
55 empty = csr_ops->read_csr_e_stat(csr, bank->bank_number); in adf_ring_show()
60 seq_printf(sfile, "ring num %d, bank num %d\n", in adf_ring_show()
61 ring->ring_number, ring->bank->bank_number); in adf_ring_show()
104 ring->bank->bank_debug_dir, in adf_ring_debugfs_add()
121 struct adf_etr_bank_data *bank = sfile->private; in adf_bank_start() local
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Dadf_gen2_hw_data.h28 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
29 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
31 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
32 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
34 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
35 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
37 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ argument
38 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
40 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ argument
45 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
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Dadf_gen2_hw_data.c63 static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_head() argument
65 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); in read_csr_ring_head()
68 static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_head() argument
71 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); in write_csr_ring_head()
74 static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_tail() argument
76 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); in read_csr_ring_tail()
79 static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_tail() argument
82 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); in write_csr_ring_tail()
85 static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank) in read_csr_e_stat() argument
87 return READ_CSR_E_STAT(csr_base_addr, bank); in read_csr_e_stat()
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/Linux-v5.15/drivers/pinctrl/stm32/
Dpinctrl-stm32.c153 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank, in stm32_gpio_backup_value() argument
156 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); in stm32_gpio_backup_value()
157 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; in stm32_gpio_backup_value()
160 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_mode() argument
163 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | in stm32_gpio_backup_mode()
165 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT; in stm32_gpio_backup_mode()
166 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT; in stm32_gpio_backup_mode()
169 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_driving() argument
172 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE); in stm32_gpio_backup_driving()
173 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE; in stm32_gpio_backup_driving()
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/Linux-v5.15/drivers/net/phy/mscc/
Dmscc_macsec.c23 enum macsec_bank bank, u32 reg) in vsc8584_macsec_phy_read() argument
34 MSCC_PHY_MACSEC_20_TARGET(bank >> 2)); in vsc8584_macsec_phy_read()
36 if (bank >> 2 == 0x1) in vsc8584_macsec_phy_read()
38 bank &= 0x3; in vsc8584_macsec_phy_read()
40 bank = 0; in vsc8584_macsec_phy_read()
45 MSCC_PHY_MACSEC_19_TARGET(bank)); in vsc8584_macsec_phy_read()
62 enum macsec_bank bank, u32 reg, u32 val) in vsc8584_macsec_phy_write() argument
72 MSCC_PHY_MACSEC_20_TARGET(bank >> 2)); in vsc8584_macsec_phy_write()
74 if ((bank >> 2 == 0x1) || (bank >> 2 == 0x3)) in vsc8584_macsec_phy_write()
75 bank &= 0x3; in vsc8584_macsec_phy_write()
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/Linux-v5.15/drivers/bus/
Duniphier-system-bus.c23 #define UNIPHIER_SBC_STRIDE 0x10 /* register stride to next bank */
25 #define UNIPHIER_SBC_BASE_DUMMY 0xffffffff /* data to squash bank 0, 1 */
35 struct uniphier_system_bus_bank bank[UNIPHIER_SBC_NR_BANKS]; member
39 int bank, u32 addr, u64 paddr, u32 size) in uniphier_system_bus_add_bank() argument
44 "range found: bank = %d, addr = %08x, paddr = %08llx, size = %08x\n", in uniphier_system_bus_add_bank()
45 bank, addr, paddr, size); in uniphier_system_bus_add_bank()
47 if (bank >= ARRAY_SIZE(priv->bank)) { in uniphier_system_bus_add_bank()
48 dev_err(priv->dev, "unsupported bank number %d\n", bank); in uniphier_system_bus_add_bank()
52 if (priv->bank[bank].base || priv->bank[bank].end) { in uniphier_system_bus_add_bank()
54 "range for bank %d has already been specified\n", bank); in uniphier_system_bus_add_bank()
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/Linux-v5.15/arch/arm/mach-s3c/
Diotiming-s3c2412.c41 unsigned int bank; in s3c2412_print_timing() local
43 for (bank = 0; bank < MAX_BANKS; bank++) { in s3c2412_print_timing()
44 bt = iot->bank[bank].io_2412; in s3c2412_print_timing()
49 "wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n", pfx, bank, in s3c2412_print_timing()
87 * s3c2412_calc_bank - calculate the bank divisor settings.
89 * @bt: The bank timing.
108 * s3c2412_iotiming_debugfs - debugfs show io bank timing information
111 * @iob: The IO bank information to decode.
131 * s3c2412_iotiming_calc - calculate all the bank divisor settings.
133 * @iot: The bank timing information.
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Diotiming-s3c2410.c27 * s3c2410_print_timing - print bank timing data for debug purposes
35 int bank; in s3c2410_print_timing() local
37 for (bank = 0; bank < MAX_BANKS; bank++) { in s3c2410_print_timing()
38 bt = timings->bank[bank].io_2410; in s3c2410_print_timing()
43 "Tcoh=%d.%d, Tcah=%d.%d\n", pfx, bank, in s3c2410_print_timing()
53 * bank_reg - convert bank number to pointer to the control register.
54 * @bank: The IO bank number.
56 static inline void __iomem *bank_reg(unsigned int bank) in bank_reg() argument
58 return S3C2410_BANKCON0 + (bank << 2); in bank_reg()
62 * bank_is_io - test whether bank is used for IO
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/Linux-v5.15/arch/x86/kernel/cpu/mce/
Damd.c122 static enum smca_bank_types smca_get_bank_type(unsigned int bank) in smca_get_bank_type() argument
126 if (bank >= MAX_NR_BANKS) in smca_get_bank_type()
129 b = &smca_banks[bank]; in smca_get_bank_type()
198 * So to define a unique name for each bank, we use a temp c-string to append
227 static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu) in smca_set_misc_banks_map() argument
235 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) in smca_set_misc_banks_map()
241 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high)) in smca_set_misc_banks_map()
245 per_cpu(smca_misc_banks_map, cpu) |= BIT(bank); in smca_set_misc_banks_map()
249 static void smca_configure(unsigned int bank, unsigned int cpu) in smca_configure() argument
254 u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); in smca_configure()
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/Linux-v5.15/drivers/dma/ipu/
Dipu_irq.c72 struct ipu_irq_bank *bank; member
96 struct ipu_irq_bank *bank; in ipu_irq_unmask() local
102 bank = map->bank; in ipu_irq_unmask()
103 if (!bank) { in ipu_irq_unmask()
109 reg = ipu_read_reg(bank->ipu, bank->control); in ipu_irq_unmask()
111 ipu_write_reg(bank->ipu, reg, bank->control); in ipu_irq_unmask()
119 struct ipu_irq_bank *bank; in ipu_irq_mask() local
125 bank = map->bank; in ipu_irq_mask()
126 if (!bank) { in ipu_irq_mask()
132 reg = ipu_read_reg(bank->ipu, bank->control); in ipu_irq_mask()
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/Linux-v5.15/drivers/pinctrl/sunxi/
Dpinctrl-sunxi.h32 #define SUNXI_PINCTRL_PIN(bank, pin) \ argument
33 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
229 * This is for the first bank. Each bank will have the same layout,
237 u8 bank = pin / PINS_PER_BANK; in sunxi_mux_reg() local
238 u32 offset = bank * BANK_MEM_SIZE; in sunxi_mux_reg()
252 u8 bank = pin / PINS_PER_BANK; in sunxi_data_reg() local
253 u32 offset = bank * BANK_MEM_SIZE; in sunxi_data_reg()
267 u8 bank = pin / PINS_PER_BANK; in sunxi_dlevel_reg() local
268 u32 offset = bank * BANK_MEM_SIZE; in sunxi_dlevel_reg()
282 u8 bank = pin / PINS_PER_BANK; in sunxi_pull_reg() local
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/Linux-v5.15/drivers/pinctrl/
Dpinctrl-rockchip.c219 * given a pin number that is local to a pin controller, find out the pin bank
220 * and the register base of the pin bank.
572 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, in rockchip_get_recalced_mux() argument
575 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_recalced_mux()
582 if (data->num == bank->bank_num && in rockchip_get_recalced_mux()
795 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, in rockchip_get_mux_route() argument
798 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux_route()
805 if ((data->bank_num == bank->bank_num) && in rockchip_get_mux_route()
820 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) in rockchip_get_mux() argument
822 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux()
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/Linux-v5.15/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-st.txt14 GPIO bank can have one of the two possible types of interrupt-wirings.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
26 Second type has a dedicated interrupt per gpio bank.
28 [irqN]----> [gpio-bank (n)]
37 bank are capable of retiming. Retiming is mainly used to improve the
39 - ranges : defines mapping between pin controller node (parent) to gpio-bank
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