Lines Matching full:bank
36 #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32))) argument
37 #define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN) argument
38 #define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA) argument
39 #define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR) argument
40 #define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC) argument
41 #define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI) argument
42 #define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK) argument
43 #define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL) argument
44 #define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT) argument
76 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_gc_to_priv() local
77 return bank->parent_priv; in brcmstb_gpio_gc_to_priv()
81 __brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank) in __brcmstb_gpio_get_active_irqs() argument
83 void __iomem *reg_base = bank->parent_priv->reg_base; in __brcmstb_gpio_get_active_irqs()
85 return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) & in __brcmstb_gpio_get_active_irqs()
86 bank->gc.read_reg(reg_base + GIO_MASK(bank->id)); in __brcmstb_gpio_get_active_irqs()
90 brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank) in brcmstb_gpio_get_active_irqs() argument
95 spin_lock_irqsave(&bank->gc.bgpio_lock, flags); in brcmstb_gpio_get_active_irqs()
96 status = __brcmstb_gpio_get_active_irqs(bank); in brcmstb_gpio_get_active_irqs()
97 spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags); in brcmstb_gpio_get_active_irqs()
103 struct brcmstb_gpio_bank *bank) in brcmstb_gpio_hwirq_to_offset() argument
105 return hwirq - (bank->gc.base - bank->parent_priv->gpio_base); in brcmstb_gpio_hwirq_to_offset()
108 static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank, in brcmstb_gpio_set_imask() argument
111 struct gpio_chip *gc = &bank->gc; in brcmstb_gpio_set_imask()
112 struct brcmstb_gpio_priv *priv = bank->parent_priv; in brcmstb_gpio_set_imask()
113 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank)); in brcmstb_gpio_set_imask()
118 imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id)); in brcmstb_gpio_set_imask()
123 gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask); in brcmstb_gpio_set_imask()
143 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_irq_mask() local
145 brcmstb_gpio_set_imask(bank, d->hwirq, false); in brcmstb_gpio_irq_mask()
151 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_irq_unmask() local
153 brcmstb_gpio_set_imask(bank, d->hwirq, true); in brcmstb_gpio_irq_unmask()
159 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_irq_ack() local
160 struct brcmstb_gpio_priv *priv = bank->parent_priv; in brcmstb_gpio_irq_ack()
161 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); in brcmstb_gpio_irq_ack()
163 gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask); in brcmstb_gpio_irq_ack()
169 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_irq_set_type() local
170 struct brcmstb_gpio_priv *priv = bank->parent_priv; in brcmstb_gpio_irq_set_type()
171 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); in brcmstb_gpio_irq_set_type()
207 spin_lock_irqsave(&bank->gc.bgpio_lock, flags); in brcmstb_gpio_irq_set_type()
209 iedge_config = bank->gc.read_reg(priv->reg_base + in brcmstb_gpio_irq_set_type()
210 GIO_EC(bank->id)) & ~mask; in brcmstb_gpio_irq_set_type()
211 iedge_insensitive = bank->gc.read_reg(priv->reg_base + in brcmstb_gpio_irq_set_type()
212 GIO_EI(bank->id)) & ~mask; in brcmstb_gpio_irq_set_type()
213 ilevel = bank->gc.read_reg(priv->reg_base + in brcmstb_gpio_irq_set_type()
214 GIO_LEVEL(bank->id)) & ~mask; in brcmstb_gpio_irq_set_type()
216 bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id), in brcmstb_gpio_irq_set_type()
218 bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id), in brcmstb_gpio_irq_set_type()
220 bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id), in brcmstb_gpio_irq_set_type()
223 spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags); in brcmstb_gpio_irq_set_type()
245 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_irq_set_wake() local
246 struct brcmstb_gpio_priv *priv = bank->parent_priv; in brcmstb_gpio_irq_set_wake()
247 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); in brcmstb_gpio_irq_set_wake()
254 bank->wake_active |= mask; in brcmstb_gpio_irq_set_wake()
256 bank->wake_active &= ~mask; in brcmstb_gpio_irq_set_wake()
272 static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank) in brcmstb_gpio_irq_bank_handler() argument
274 struct brcmstb_gpio_priv *priv = bank->parent_priv; in brcmstb_gpio_irq_bank_handler()
276 int hwbase = bank->gc.base - priv->gpio_base; in brcmstb_gpio_irq_bank_handler()
279 while ((status = brcmstb_gpio_get_active_irqs(bank))) { in brcmstb_gpio_irq_bank_handler()
283 if (offset >= bank->width) in brcmstb_gpio_irq_bank_handler()
285 "IRQ for invalid GPIO (bank=%d, offset=%d)\n", in brcmstb_gpio_irq_bank_handler()
286 bank->id, offset); in brcmstb_gpio_irq_bank_handler()
297 struct brcmstb_gpio_bank *bank; in brcmstb_gpio_irq_handler() local
303 list_for_each_entry(bank, &priv->bank_list, node) in brcmstb_gpio_irq_handler()
304 brcmstb_gpio_irq_bank_handler(bank); in brcmstb_gpio_irq_handler()
311 struct brcmstb_gpio_bank *bank; in brcmstb_gpio_hwirq_to_bank() local
315 list_for_each_entry_reverse(bank, &priv->bank_list, node) { in brcmstb_gpio_hwirq_to_bank()
316 i += bank->gc.ngpio; in brcmstb_gpio_hwirq_to_bank()
318 return bank; in brcmstb_gpio_hwirq_to_bank()
335 struct brcmstb_gpio_bank *bank = in brcmstb_gpio_irq_map() local
340 if (!bank) in brcmstb_gpio_irq_map()
343 dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n", in brcmstb_gpio_irq_map()
344 irq, (int)hwirq, bank->id); in brcmstb_gpio_irq_map()
345 ret = irq_set_chip_data(irq, &bank->gc); in brcmstb_gpio_irq_map()
373 of_property_count_u32_elems(np, "brcm,gpio-bank-widths"); in brcmstb_gpio_sanity_check_banks()
376 dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n", in brcmstb_gpio_sanity_check_banks()
387 struct brcmstb_gpio_bank *bank; in brcmstb_gpio_remove() local
411 list_for_each_entry(bank, &priv->bank_list, node) in brcmstb_gpio_remove()
412 gpiochip_remove(&bank->gc); in brcmstb_gpio_remove()
421 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_of_xlate() local
436 if (unlikely(offset >= bank->width)) { in brcmstb_gpio_of_xlate()
513 struct brcmstb_gpio_bank *bank) in brcmstb_gpio_bank_save() argument
515 struct gpio_chip *gc = &bank->gc; in brcmstb_gpio_bank_save()
519 bank->saved_regs[i] = gc->read_reg(priv->reg_base + in brcmstb_gpio_bank_save()
520 GIO_BANK_OFF(bank->id, i)); in brcmstb_gpio_bank_save()
526 struct brcmstb_gpio_bank *bank; in brcmstb_gpio_quiesce() local
534 list_for_each_entry(bank, &priv->bank_list, node) { in brcmstb_gpio_quiesce()
535 gc = &bank->gc; in brcmstb_gpio_quiesce()
538 brcmstb_gpio_bank_save(priv, bank); in brcmstb_gpio_quiesce()
542 imask = bank->wake_active; in brcmstb_gpio_quiesce()
545 gc->write_reg(priv->reg_base + GIO_MASK(bank->id), in brcmstb_gpio_quiesce()
558 struct brcmstb_gpio_bank *bank) in brcmstb_gpio_bank_restore() argument
560 struct gpio_chip *gc = &bank->gc; in brcmstb_gpio_bank_restore()
564 gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i), in brcmstb_gpio_bank_restore()
565 bank->saved_regs[i]); in brcmstb_gpio_bank_restore()
577 struct brcmstb_gpio_bank *bank; in brcmstb_gpio_resume() local
580 list_for_each_entry(bank, &priv->bank_list, node) { in brcmstb_gpio_resume()
581 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank); in brcmstb_gpio_resume()
582 brcmstb_gpio_bank_restore(priv, bank); in brcmstb_gpio_resume()
659 of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p, in brcmstb_gpio_probe()
661 struct brcmstb_gpio_bank *bank; in brcmstb_gpio_probe() local
665 * If bank_width is 0, then there is an empty bank in the in brcmstb_gpio_probe()
669 dev_dbg(dev, "Width 0 found: Empty bank @ %d\n", in brcmstb_gpio_probe()
676 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); in brcmstb_gpio_probe()
677 if (!bank) { in brcmstb_gpio_probe()
682 bank->parent_priv = priv; in brcmstb_gpio_probe()
683 bank->id = num_banks; in brcmstb_gpio_probe()
685 dev_err(dev, "Invalid bank width %d\n", bank_width); in brcmstb_gpio_probe()
689 bank->width = bank_width; in brcmstb_gpio_probe()
696 gc = &bank->gc; in brcmstb_gpio_probe()
698 reg_base + GIO_DATA(bank->id), in brcmstb_gpio_probe()
700 reg_base + GIO_IODIR(bank->id), flags); in brcmstb_gpio_probe()
716 /* not all ngpio lines are valid, will use bank width later */ in brcmstb_gpio_probe()
718 gc->offset = bank->id * MAX_GPIO_PER_BANK; in brcmstb_gpio_probe()
726 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank); in brcmstb_gpio_probe()
727 gc->write_reg(reg_base + GIO_MASK(bank->id), 0); in brcmstb_gpio_probe()
729 err = gpiochip_add_data(gc, bank); in brcmstb_gpio_probe()
731 dev_err(dev, "Could not add gpiochip for bank %d\n", in brcmstb_gpio_probe()
732 bank->id); in brcmstb_gpio_probe()
737 dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id, in brcmstb_gpio_probe()
738 gc->base, gc->ngpio, bank->width); in brcmstb_gpio_probe()
740 /* Everything looks good, so add bank to list */ in brcmstb_gpio_probe()
741 list_add(&bank->node, &priv->bank_list); in brcmstb_gpio_probe()