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/Linux-v5.15/drivers/pinctrl/samsung/
Dpinctrl-samsung.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
57 * enum eint_type - possible external interrupt types.
58 * @EINT_TYPE_NONE: bank does not support external interrupts
59 * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
60 * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
61 * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-st.txt3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
14 GPIO bank can have one of the two possible types of interrupt-wirings.
17 reduces number of overall interrupts numbers required. All these banks belong to
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
26 Second type has a dedicated interrupt per gpio bank.
[all …]
Dmicrochip,sparx5-sgpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
14 the number of available GPIOs with a minimum number of additional
21 pattern: "^gpio@[0-9a-f]+$"
25 - microchip,sparx5-sgpio
26 - mscc,ocelot-sgpio
27 - mscc,luton-sgpio
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Dallwinner,sun4i-a10-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/allwinner,sun4i-a10-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#gpio-cells":
17 GPIO consumers must use three arguments, first the number of the
18 bank, then the pin number inside that bank, and finally the GPIO
21 "#interrupt-cells":
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/Linux-v5.15/drivers/gpio/
Dgpio-zynq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
20 #define DRIVER_NAME "zynq-gpio"
46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
61 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
64 /* LSW Mask & Data -WO */
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/Linux-v5.15/drivers/pinctrl/
Dpinctrl-rockchip.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2020-2021 Rockchip Electronics Co. Ltd.
8 * With some ideas taken from pinctrl-samsung:
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
74 * @offset: if initialized to -1 it will be autocalculated, by specifying
107 * @offset: if initialized to -1 it will be autocalculated, by specifying
120 * @dev: the pinctrl device bind to the bank
121 * @reg_base: register base of the gpio bank
123 * @clk: clock of the gpio bank
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Dpinctrl-equilibrium.h1 /* SPDX-License-Identifier: GPL-2.0 */
18 #define DRV_CUR_PINS 16 /* Drive Current pin number per register */
74 * @nr_groups: number of groups included in @groups.
83 * struct eqbr_pin_bank: represent a pin bank.
84 * @membase: base address of the pin bank register.
85 * @id: bank id, to idenify the unique bank.
86 * @pin_base: starting pin number of the pin bank.
87 * @nr_pins: number of the pins of the pin bank.
88 * @aval_pinmap: available pin bitmap of the pin bank.
101 * @bank: pointer to corresponding pin bank.
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Dpinctrl-at91-pio4.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/pinctrl/at91.h>
18 #include <linux/pinctrl/pinconf-generic.h>
24 #include "pinctrl-utils.h"
30 * designed the pin id into this bank.
76 * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct
77 * @nbanks: number of PIO banks
78 * @last_bank_count: number of lines in the last bank (can be less than
97 unsigned int bank; member
103 * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio)
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Dpinctrl-equilibrium.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pinctrl/pinconf-generic.h>
18 #include "pinctrl-equilibrium.h"
20 #define PIN_NAME_FMT "io-%d"
31 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
32 writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR); in eqbr_gpio_disable_irq()
33 raw_spin_unlock_irqrestore(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
43 gc->direction_input(gc, offset); in eqbr_gpio_enable_irq()
44 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_enable_irq()
45 writel(BIT(offset), gctrl->membase + GPIO_IRNRNSET); in eqbr_gpio_enable_irq()
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/Linux-v5.15/drivers/thermal/
Dmtk_thermal.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/nvmem-consumer.h>
103 /* The total number of temperature sensors in the MT8173 */
106 /* The number of banks in the MT8173 */
109 /* The number of sensing points per bank */
112 /* The number of controller in the MT8173 */
176 /* The total number of temperature sensors in the MT2701 */
179 /* The number of sensing points per bank */
182 /* The number of controller in the MT2701 */
197 /* The total number of temperature sensors in the MT2712 */
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/Linux-v5.15/Documentation/hwmon/
Dabituguru-datasheet.rst14 Olle Sandberg <ollebull@gmail.com>, 2005-05-25
27 Hans de Goede <j.w.r.degoede@hhs.nl>, 28-01-2006
33 As far as known the uGuru is always placed at and using the (ISA) I/O-ports
34 0xE0 and 0xE4, so we don't have to scan any port-range, just check what the two
35 ports are holding for detection. We will refer to 0xE0 as CMD (command-port)
39 present. We have to check for two different values at data-port, because
41 later on attached again data-port will hold 0x08, more about this later.
57 ----------
59 The uGuru has a number of different addressing levels. The first addressing
60 level we will call banks. A bank holds data for one or more sensors. The data
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/Linux-v5.15/drivers/dma/ipu/
Dipu_irq.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/dma/ipu-dma.h>
20 * Register read / write - shall be inlined by the compiler
24 return __raw_readl(ipu->reg_ipu + reg); in ipu_read_reg()
29 __raw_writel(value, ipu->reg_ipu + reg); in ipu_write_reg()
72 struct ipu_irq_bank *bank; member
96 struct ipu_irq_bank *bank; in ipu_irq_unmask() local
102 bank = map->bank; in ipu_irq_unmask()
103 if (!bank) { in ipu_irq_unmask()
105 pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq); in ipu_irq_unmask()
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/Linux-v5.15/drivers/mtd/nand/raw/
Ddenali.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (c) 2009 - 2010, Intel Corporation and its suppliers.
18 #define DEVICE_RESET__BANK(bank) BIT(bank) argument
36 #define RB_PIN_ENABLED__BANK(bank) BIT(bank) argument
208 #define INTR_STATUS(bank) (0x410 + (bank) * 0x50) argument
209 #define INTR_EN(bank) (0x420 + (bank) * 0x50) argument
230 #define PAGE_CNT(bank) (0x430 + (bank) * 0x50) argument
231 #define ERR_PAGE_ADDR(bank) (0x440 + (bank) * 0x50) argument
232 #define ERR_BLOCK_ADDR(bank) (0x450 + (bank) * 0x50) argument
254 #define ECC_COR_INFO(bank) (0x650 + (bank) / 2 * 0x10) argument
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/Linux-v5.15/drivers/mtd/devices/
Dspear_smi.c157 * struct spear_smi - Structure for SMI Device
165 * @cmd_complete: queue to wait for command completion of NOR-flash.
166 * @num_flashes: number of flashes actually present on board.
167 * @flash: separate structure for each Serial NOR-flash attached to SMI.
182 * struct spear_snor_flash - Structure for Serial NOR Flash
184 * @bank: Bank number(0, 1, 2, 3) for each NOR-flash.
185 * @dev_id: Device ID of NOR-flash.
187 * @mtd: MTD info for each NOR-flash.
188 * @num_parts: Total number of partition in each bank of NOR-flash.
189 * @parts: Partition info for each bank of NOR-flash.
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Dgpio.txt1 Every GPIO controller node must have #gpio-cells property defined,
2 this information will be used to translate gpio-specifiers.
10 - compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
13 - #gpio-cells : Should be two. The first cell is the pin number and the
15 - gpio-controller : Marks the port as GPIO controller.
17 - fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
20 - interrupts : This property provides the list of interrupt for each GPIO having
21 one as described by the fsl,cpm1-gpio-irq-mask property. There should be as
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/Linux-v5.15/Documentation/devicetree/bindings/mtd/
Dfsmc-nand.txt5 - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
6 - reg : Address range of the mtd chip
7 - reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd"
10 - bank-width : Width (in bytes) of the device. If not present, the width
12 - nand-skip-bbtscan: Indicates the BBT scanning should be skipped
13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
15 byte 0 TCLR : CLE to RE delay in number of AHB clock cycles, only 4 bits
19 byte 2 THIZ : number of HCLK clock cycles during which the data bus is
20 kept in Hi-Z (tristate) after the start of a write access.
23 byte 3 THOLD : number of HCLK clock cycles to hold the address (and data
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/Linux-v5.15/drivers/memory/
Djz4780-nemc.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Author: Alex Smith <alex@alex-smith.me.uk>
21 #include <linux/jz4780-nemc.h>
23 #define NEMC_SMCRn(n) (0x14 + (((n) - 1) * 4))
43 #define NEMC_NFCSR_NFEn(n) BIT(((n) - 1) << 1)
44 #define NEMC_NFCSR_NFCEn(n) BIT((((n) - 1) << 1) + 1)
45 #define NEMC_NFCSR_TNFEn(n) BIT(16 + (n) - 1)
62 * jz4780_nemc_num_banks() - count the number of banks referenced by a device
65 * Return: The number of unique NEMC banks referred to by the specified NEMC
66 * child device. Unique here means that a device that references the same bank
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/Linux-v5.15/Documentation/devicetree/bindings/gpio/
Dbrcm,brcmstb-gpio.txt3 The controller's registers are organized as sets of eight 32-bit
4 registers with each set controlling a bank of up to 32 pins. A single
9 - compatible:
10 Must be "brcm,brcmstb-gpio"
12 - reg:
16 - #gpio-cells:
17 Should be <2>. The first cell is the pin number (within the controller's
19 bit[0]: polarity (0 for active-high, 1 for active-low)
21 - gpio-controller:
24 - brcm,gpio-bank-widths:
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/Linux-v5.15/arch/arm/mach-omap2/
Dpowerdomain.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc.
6 * Copyright (C) 2007-2011 Nokia Corporation
10 * XXX This should be moved to the mach-omap2/ directory at the earliest
45 * PWRDM_HAS_HDWR_SAR - powerdomain has hardware save-and-restore support
47 * PWRDM_HAS_MPU_QUIRK - MPU pwr domain has MEM bank 0 bits in MEM
48 * bank 1 position. This is true for OMAP3430
50 * PWRDM_HAS_LOWPOWERSTATECHANGE - can transition from a sleep state
58 * Number of memory banks that are power-controllable. On OMAP4430, the
64 * Maximum number of clockdomains that can be associated with a powerdomain.
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Dpowerdomain.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
6 * Copyright (C) 2007-2011 Nokia Corporation
72 if (!strcmp(name, temp_pwrdm->name)) { in _pwrdm_lookup()
82 * _pwrdm_register - register a powerdomain
86 * -EINVAL if given a null pointer, -EEXIST if a powerdomain is
94 if (!pwrdm || !pwrdm->name) in _pwrdm_register()
95 return -EINVAL; in _pwrdm_register()
98 pwrdm->prcm_partition == OMAP4430_INVALID_PRCM_PARTITION) { in _pwrdm_register()
100 pwrdm->name); in _pwrdm_register()
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/Linux-v5.15/arch/powerpc/platforms/chrp/
Dgg2.h2 * include/asm-ppc/gg2.h -- VLSI VAS96011/12 `Golden Gate 2' register definitions
29 #define GG2_ROM_BASE0 0xff000000 /* ROM bank 0 */
30 #define GG2_ROM_BASE1 0xff800000 /* ROM bank 1 */
39 #define GG2_PCI_BUSNO 0x40 /* Bus number */
40 #define GG2_PCI_SUBBUSNO 0x41 /* Subordinate bus number */
48 #define GG2_PCI_DRAM_BANK0 0x90 /* Control register for DRAM bank #0 */
49 #define GG2_PCI_DRAM_BANK1 0x94 /* Control register for DRAM bank #1 */
50 #define GG2_PCI_DRAM_BANK2 0x98 /* Control register for DRAM bank #2 */
51 #define GG2_PCI_DRAM_BANK3 0x9c /* Control register for DRAM bank #3 */
52 #define GG2_PCI_DRAM_BANK4 0xa0 /* Control register for DRAM bank #4 */
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/Linux-v5.15/arch/x86/include/uapi/asm/
Dmce.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
14 __u64 status; /* Bank's MCi_STATUS MSR */
15 __u64 misc; /* Bank's MCi_MISC MSR */
16 __u64 addr; /* Bank's MCi_ADDR MSR */
27 __u8 bank; /* Machine check bank reporting the error */ member
28 __u8 cpu; /* CPU number; obsoleted by extcpu */
30 __u32 extcpu; /* Linux CPU number that detected the error */
36 __u64 ppin; /* Protected Processor Inventory Number */
/Linux-v5.15/Documentation/devicetree/bindings/memory-controllers/
Dexynos-srom.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
19 - const: samsung,exynos4210-srom
24 "#address-cells":
27 "#size-cells":
34 Reflects the memory layout with four integer values per bank. Format:
35 <bank-number> 0 <parent address of bank> <size>
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/Linux-v5.15/include/linux/soundwire/
Dsdw.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
15 /* SDW Broadcast Device Number */
18 /* SDW Enumeration Device Number */
25 /* SDW Master Device Number, not supported yet */
71 * enum sdw_slave_status - Slave status
89 * @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepare
90 * @SDW_CLK_POST_DEPREPARE: post clock stop de-prepare
100 * enum sdw_command_response - Command response as defined by SDW spec
186 * enum sdw_p15_behave - Slave Port 15 behaviour when the Master attempts a
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/Linux-v5.15/drivers/crypto/qat/qat_common/
Dadf_transport.c1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
2 /* Copyright(c) 2014 - 2020 Intel Corporation */
16 return data - mult; in adf_modulo()
21 if (((size - 1) & addr) != 0) in adf_check_ring_alignment()
22 return -EFAULT; in adf_check_ring_alignment()
37 static int adf_reserve_ring(struct adf_etr_bank_data *bank, u32 ring) in adf_reserve_ring() argument
39 spin_lock(&bank->lock); in adf_reserve_ring()
40 if (bank->ring_mask & (1 << ring)) { in adf_reserve_ring()
41 spin_unlock(&bank->lock); in adf_reserve_ring()
42 return -EFAULT; in adf_reserve_ring()
[all …]

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