Lines Matching +full:bank +full:- +full:number
1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/pinctrl/at91.h>
18 #include <linux/pinctrl/pinconf-generic.h>
24 #include "pinctrl-utils.h"
30 * designed the pin id into this bank.
76 * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct
77 * @nbanks: number of PIO banks
78 * @last_bank_count: number of lines in the last bank (can be less than
97 unsigned int bank; member
103 * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio)
106 * @nbanks: number of PIO groups, it can vary depending on the SoC.
111 * @pins: pins table used for both pinctrl and gpio. pin_id, bank and line
114 * @npins: number of pins.
117 * @irqs: table containing the hw irq number of the bank. The index of the
118 * table is the bank id.
153 {"atmel,drive-strength", ATMEL_PIN_CONFIG_DRIVE_STRENGTH, 0},
156 /* --- GPIO --- */
158 unsigned int bank, unsigned int reg) in atmel_gpio_read() argument
160 return readl_relaxed(atmel_pioctrl->reg_base in atmel_gpio_read()
161 + ATMEL_PIO_BANK_OFFSET * bank + reg); in atmel_gpio_read()
165 unsigned int bank, unsigned int reg, in atmel_gpio_write() argument
168 writel_relaxed(val, atmel_pioctrl->reg_base in atmel_gpio_write()
169 + ATMEL_PIO_BANK_OFFSET * bank + reg); in atmel_gpio_write()
183 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; in atmel_gpio_irq_set_type()
186 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, in atmel_gpio_irq_set_type()
187 BIT(pin->line)); in atmel_gpio_irq_set_type()
188 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); in atmel_gpio_irq_set_type()
214 return -EINVAL; in atmel_gpio_irq_set_type()
217 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); in atmel_gpio_irq_set_type()
225 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; in atmel_gpio_irq_mask()
227 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR, in atmel_gpio_irq_mask()
228 BIT(pin->line)); in atmel_gpio_irq_mask()
234 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; in atmel_gpio_irq_unmask()
236 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER, in atmel_gpio_irq_unmask()
237 BIT(pin->line)); in atmel_gpio_irq_unmask()
245 int bank = ATMEL_PIO_BANK(d->hwirq); in atmel_gpio_irq_set_wake() local
246 int line = ATMEL_PIO_LINE(d->hwirq); in atmel_gpio_irq_set_wake()
248 /* The gpio controller has one interrupt line per bank. */ in atmel_gpio_irq_set_wake()
249 irq_set_irq_wake(atmel_pioctrl->irqs[bank], on); in atmel_gpio_irq_set_wake()
252 atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line); in atmel_gpio_irq_set_wake()
254 atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line)); in atmel_gpio_irq_set_wake()
275 return irq_find_mapping(atmel_pioctrl->irq_domain, offset); in atmel_gpio_to_irq()
284 int n, bank = -1; in atmel_gpio_irq_handler() local
286 /* Find from which bank is the irq received. */ in atmel_gpio_irq_handler()
287 for (n = 0; n < atmel_pioctrl->nbanks; n++) { in atmel_gpio_irq_handler()
288 if (atmel_pioctrl->irqs[n] == irq) { in atmel_gpio_irq_handler()
289 bank = n; in atmel_gpio_irq_handler()
294 if (bank < 0) { in atmel_gpio_irq_handler()
295 dev_err(atmel_pioctrl->dev, in atmel_gpio_irq_handler()
296 "no bank associated to irq %u\n", irq); in atmel_gpio_irq_handler()
303 isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank, in atmel_gpio_irq_handler()
305 isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank, in atmel_gpio_irq_handler()
312 atmel_pioctrl->gpio_chip, in atmel_gpio_irq_handler()
313 bank * ATMEL_PIO_NPINS_PER_BANK + n)); in atmel_gpio_irq_handler()
323 struct atmel_pin *pin = atmel_pioctrl->pins[offset]; in atmel_gpio_direction_input()
326 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, in atmel_gpio_direction_input()
327 BIT(pin->line)); in atmel_gpio_direction_input()
328 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); in atmel_gpio_direction_input()
330 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); in atmel_gpio_direction_input()
338 struct atmel_pin *pin = atmel_pioctrl->pins[offset]; in atmel_gpio_get()
341 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR); in atmel_gpio_get()
343 return !!(reg & BIT(pin->line)); in atmel_gpio_get()
350 unsigned int bank; in atmel_gpio_get_multiple() local
352 bitmap_zero(bits, atmel_pioctrl->npins); in atmel_gpio_get_multiple()
354 for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) { in atmel_gpio_get_multiple()
355 unsigned int word = bank; in atmel_gpio_get_multiple()
360 word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK); in atmel_gpio_get_multiple()
361 offset = bank * ATMEL_PIO_NPINS_PER_BANK % BITS_PER_LONG; in atmel_gpio_get_multiple()
366 reg = atmel_gpio_read(atmel_pioctrl, bank, ATMEL_PIO_PDSR); in atmel_gpio_get_multiple()
378 struct atmel_pin *pin = atmel_pioctrl->pins[offset]; in atmel_gpio_direction_output()
381 atmel_gpio_write(atmel_pioctrl, pin->bank, in atmel_gpio_direction_output()
383 BIT(pin->line)); in atmel_gpio_direction_output()
385 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, in atmel_gpio_direction_output()
386 BIT(pin->line)); in atmel_gpio_direction_output()
387 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); in atmel_gpio_direction_output()
389 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); in atmel_gpio_direction_output()
397 struct atmel_pin *pin = atmel_pioctrl->pins[offset]; in atmel_gpio_set()
399 atmel_gpio_write(atmel_pioctrl, pin->bank, in atmel_gpio_set()
401 BIT(pin->line)); in atmel_gpio_set()
408 unsigned int bank; in atmel_gpio_set_multiple() local
410 for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) { in atmel_gpio_set_multiple()
412 unsigned int word = bank; in atmel_gpio_set_multiple()
415 * On a 64-bit platform, BITS_PER_LONG is 64 so it is necessary to iterate over in atmel_gpio_set_multiple()
419 word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK); in atmel_gpio_set_multiple()
425 atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_SODR, bitmask); in atmel_gpio_set_multiple()
428 atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_CODR, bitmask); in atmel_gpio_set_multiple()
448 /* --- PINCTRL --- */
453 unsigned int bank = atmel_pioctrl->pins[pin_id]->bank; in atmel_pin_config_read() local
454 unsigned int line = atmel_pioctrl->pins[pin_id]->line; in atmel_pin_config_read()
455 void __iomem *addr = atmel_pioctrl->reg_base in atmel_pin_config_read()
456 + bank * ATMEL_PIO_BANK_OFFSET; in atmel_pin_config_read()
469 unsigned int bank = atmel_pioctrl->pins[pin_id]->bank; in atmel_pin_config_write() local
470 unsigned int line = atmel_pioctrl->pins[pin_id]->line; in atmel_pin_config_write()
471 void __iomem *addr = atmel_pioctrl->reg_base in atmel_pin_config_write()
472 + bank * ATMEL_PIO_BANK_OFFSET; in atmel_pin_config_write()
484 return atmel_pioctrl->npins; in atmel_pctl_get_groups_count()
492 return atmel_pioctrl->groups[selector].name; in atmel_pctl_get_group_name()
502 *pins = (unsigned int *)&atmel_pioctrl->groups[selector].pin; in atmel_pctl_get_group_pins()
514 for (i = 0; i < atmel_pioctrl->npins; i++) { in atmel_pctl_find_group_by_pin()
515 struct atmel_group *grp = atmel_pioctrl->groups + i; in atmel_pctl_find_group_by_pin()
517 if (grp->pin == pin) in atmel_pctl_find_group_by_pin()
537 return -EINVAL; in atmel_pctl_xlate_pinfunc()
543 return -EINVAL; in atmel_pctl_xlate_pinfunc()
544 *grp_name = grp->name; in atmel_pctl_xlate_pinfunc()
546 atmel_pioctrl->pins[pin_id]->mux = func_id; in atmel_pctl_xlate_pinfunc()
547 atmel_pioctrl->pins[pin_id]->ioset = ATMEL_GET_PIN_IOSET(pinfunc); in atmel_pctl_xlate_pinfunc()
549 if (np->parent == atmel_pioctrl->node) in atmel_pctl_xlate_pinfunc()
550 atmel_pioctrl->pins[pin_id]->device = np->name; in atmel_pctl_xlate_pinfunc()
552 atmel_pioctrl->pins[pin_id]->device = np->parent->name; in atmel_pctl_xlate_pinfunc()
571 return -EINVAL; in atmel_pctl_dt_subnode_to_map()
576 dev_err(pctldev->dev, "%pOF: could not parse node property\n", in atmel_pctl_dt_subnode_to_map()
581 num_pins = pins->length / sizeof(u32); in atmel_pctl_dt_subnode_to_map()
583 dev_err(pctldev->dev, "no pins found in node %pOF\n", np); in atmel_pctl_dt_subnode_to_map()
584 ret = -EINVAL; in atmel_pctl_dt_subnode_to_map()
664 dev_err(pctldev->dev, "can't create maps for node %pOF\n", in atmel_pctl_dt_node_to_map()
697 *groups = atmel_pioctrl->group_names; in atmel_pmx_get_function_groups()
698 *num_groups = atmel_pioctrl->npins; in atmel_pmx_get_function_groups()
711 dev_dbg(pctldev->dev, "enable function %s group %s\n", in atmel_pmx_set_mux()
712 atmel_functions[function], atmel_pioctrl->groups[group].name); in atmel_pmx_set_mux()
714 pin = atmel_pioctrl->groups[group].pin; in atmel_pmx_set_mux()
718 dev_dbg(pctldev->dev, "pin: %u, conf: 0x%08x\n", pin, conf); in atmel_pmx_set_mux()
737 struct atmel_group *grp = atmel_pioctrl->groups + group; in atmel_conf_pin_config_group_get()
738 unsigned int pin_id = grp->pin; in atmel_conf_pin_config_group_get()
746 return -EINVAL; in atmel_conf_pin_config_group_get()
752 return -EINVAL; in atmel_conf_pin_config_group_get()
758 return -EINVAL; in atmel_conf_pin_config_group_get()
763 return -EINVAL; in atmel_conf_pin_config_group_get()
768 return -EINVAL; in atmel_conf_pin_config_group_get()
772 if (!atmel_pioctrl->slew_rate_support) in atmel_conf_pin_config_group_get()
773 return -EOPNOTSUPP; in atmel_conf_pin_config_group_get()
775 return -EINVAL; in atmel_conf_pin_config_group_get()
780 return -EINVAL; in atmel_conf_pin_config_group_get()
784 return -ENOTSUPP; in atmel_conf_pin_config_group_get()
797 struct atmel_group *grp = atmel_pioctrl->groups + group; in atmel_conf_pin_config_group_set()
798 unsigned int bank, pin, pin_id = grp->pin; in atmel_conf_pin_config_group_set() local
805 if (atmel_pioctrl->slew_rate_support) in atmel_conf_pin_config_group_set()
812 dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n", in atmel_conf_pin_config_group_set()
847 * - can't have different debounce periods inside a same group, in atmel_conf_pin_config_group_set()
848 * - the register to configure this period is a secure register. in atmel_conf_pin_config_group_set()
858 bank = ATMEL_PIO_BANK(pin_id); in atmel_conf_pin_config_group_set()
863 writel_relaxed(mask, atmel_pioctrl->reg_base + in atmel_conf_pin_config_group_set()
864 bank * ATMEL_PIO_BANK_OFFSET + in atmel_conf_pin_config_group_set()
867 writel_relaxed(mask, atmel_pioctrl->reg_base + in atmel_conf_pin_config_group_set()
868 bank * ATMEL_PIO_BANK_OFFSET + in atmel_conf_pin_config_group_set()
873 if (!atmel_pioctrl->slew_rate_support) in atmel_conf_pin_config_group_set()
888 dev_warn(pctldev->dev, "drive strength not updated (incorrect value)\n"); in atmel_conf_pin_config_group_set()
892 dev_warn(pctldev->dev, in atmel_conf_pin_config_group_set()
899 dev_dbg(pctldev->dev, "%s: reg=0x%08x\n", __func__, conf); in atmel_conf_pin_config_group_set()
912 if (!atmel_pioctrl->pins[pin_id]->device) in atmel_conf_pin_config_dbg_show()
915 if (atmel_pioctrl->pins[pin_id]) in atmel_conf_pin_config_dbg_show()
917 atmel_pioctrl->pins[pin_id]->device, in atmel_conf_pin_config_dbg_show()
918 atmel_pioctrl->pins[pin_id]->ioset); in atmel_conf_pin_config_dbg_show()
922 seq_printf(s, "%s ", "pull-up"); in atmel_conf_pin_config_dbg_show()
924 seq_printf(s, "%s ", "pull-down"); in atmel_conf_pin_config_dbg_show()
928 seq_printf(s, "%s ", "open-drain"); in atmel_conf_pin_config_dbg_show()
931 if (atmel_pioctrl->slew_rate_support && (conf & ATMEL_PIO_SR_MASK)) in atmel_conf_pin_config_dbg_show()
932 seq_printf(s, "%s ", "slew-rate"); in atmel_conf_pin_config_dbg_show()
936 seq_printf(s, "%s ", "medium-drive"); in atmel_conf_pin_config_dbg_show()
939 seq_printf(s, "%s ", "high-drive"); in atmel_conf_pin_config_dbg_show()
943 seq_printf(s, "%s ", "low-drive"); in atmel_conf_pin_config_dbg_show()
967 * For each bank, save IMR to restore it later and disable all GPIO in atmel_pctrl_suspend()
970 for (i = 0; i < atmel_pioctrl->nbanks; i++) { in atmel_pctrl_suspend()
971 atmel_pioctrl->pm_suspend_backup[i].imr = in atmel_pctrl_suspend()
974 ~atmel_pioctrl->pm_wakeup_sources[i]); in atmel_pctrl_suspend()
975 atmel_pioctrl->pm_suspend_backup[i].odsr = in atmel_pctrl_suspend()
980 atmel_pioctrl->pm_suspend_backup[i].cfgr[j] = in atmel_pctrl_suspend()
994 for (i = 0; i < atmel_pioctrl->nbanks; i++) { in atmel_pctrl_resume()
996 atmel_pioctrl->pm_suspend_backup[i].imr); in atmel_pctrl_resume()
998 atmel_pioctrl->pm_suspend_backup[i].odsr); in atmel_pctrl_resume()
1003 atmel_pioctrl->pm_suspend_backup[i].cfgr[j]); in atmel_pctrl_resume()
1015 * The number of banks can be different from a SoC to another one.
1031 .compatible = "atmel,sama5d2-pinctrl",
1034 .compatible = "microchip,sama7g5-pinctrl",
1043 struct device *dev = &pdev->dev; in atmel_pinctrl_probe()
1054 return -ENOMEM; in atmel_pinctrl_probe()
1055 atmel_pioctrl->dev = dev; in atmel_pinctrl_probe()
1056 atmel_pioctrl->node = dev->of_node; in atmel_pinctrl_probe()
1059 match = of_match_node(atmel_pctrl_of_match, dev->of_node); in atmel_pinctrl_probe()
1062 return -ENODEV; in atmel_pinctrl_probe()
1064 atmel_pioctrl_data = match->data; in atmel_pinctrl_probe()
1065 atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks; in atmel_pinctrl_probe()
1066 atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK; in atmel_pinctrl_probe()
1067 /* if last bank has limited number of pins, adjust accordingly */ in atmel_pinctrl_probe()
1068 if (atmel_pioctrl_data->last_bank_count != ATMEL_PIO_NPINS_PER_BANK) { in atmel_pinctrl_probe()
1069 atmel_pioctrl->npins -= ATMEL_PIO_NPINS_PER_BANK; in atmel_pinctrl_probe()
1070 atmel_pioctrl->npins += atmel_pioctrl_data->last_bank_count; in atmel_pinctrl_probe()
1072 atmel_pioctrl->slew_rate_support = atmel_pioctrl_data->slew_rate_support; in atmel_pinctrl_probe()
1074 atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0); in atmel_pinctrl_probe()
1075 if (IS_ERR(atmel_pioctrl->reg_base)) in atmel_pinctrl_probe()
1076 return PTR_ERR(atmel_pioctrl->reg_base); in atmel_pinctrl_probe()
1078 atmel_pioctrl->clk = devm_clk_get(dev, NULL); in atmel_pinctrl_probe()
1079 if (IS_ERR(atmel_pioctrl->clk)) { in atmel_pinctrl_probe()
1081 return PTR_ERR(atmel_pioctrl->clk); in atmel_pinctrl_probe()
1084 atmel_pioctrl->pins = devm_kcalloc(dev, in atmel_pinctrl_probe()
1085 atmel_pioctrl->npins, in atmel_pinctrl_probe()
1086 sizeof(*atmel_pioctrl->pins), in atmel_pinctrl_probe()
1088 if (!atmel_pioctrl->pins) in atmel_pinctrl_probe()
1089 return -ENOMEM; in atmel_pinctrl_probe()
1091 pin_desc = devm_kcalloc(dev, atmel_pioctrl->npins, sizeof(*pin_desc), in atmel_pinctrl_probe()
1094 return -ENOMEM; in atmel_pinctrl_probe()
1096 atmel_pinctrl_desc.npins = atmel_pioctrl->npins; in atmel_pinctrl_probe()
1102 atmel_pioctrl->npins, sizeof(*group_names), in atmel_pinctrl_probe()
1105 return -ENOMEM; in atmel_pinctrl_probe()
1106 atmel_pioctrl->group_names = group_names; in atmel_pinctrl_probe()
1108 atmel_pioctrl->groups = devm_kcalloc(&pdev->dev, in atmel_pinctrl_probe()
1109 atmel_pioctrl->npins, sizeof(*atmel_pioctrl->groups), in atmel_pinctrl_probe()
1111 if (!atmel_pioctrl->groups) in atmel_pinctrl_probe()
1112 return -ENOMEM; in atmel_pinctrl_probe()
1113 for (i = 0 ; i < atmel_pioctrl->npins; i++) { in atmel_pinctrl_probe()
1114 struct atmel_group *group = atmel_pioctrl->groups + i; in atmel_pinctrl_probe()
1115 unsigned int bank = ATMEL_PIO_BANK(i); in atmel_pinctrl_probe() local
1118 atmel_pioctrl->pins[i] = devm_kzalloc(dev, in atmel_pinctrl_probe()
1119 sizeof(**atmel_pioctrl->pins), GFP_KERNEL); in atmel_pinctrl_probe()
1120 if (!atmel_pioctrl->pins[i]) in atmel_pinctrl_probe()
1121 return -ENOMEM; in atmel_pinctrl_probe()
1123 atmel_pioctrl->pins[i]->pin_id = i; in atmel_pinctrl_probe()
1124 atmel_pioctrl->pins[i]->bank = bank; in atmel_pinctrl_probe()
1125 atmel_pioctrl->pins[i]->line = line; in atmel_pinctrl_probe()
1127 pin_desc[i].number = i; in atmel_pinctrl_probe()
1130 bank + 'A', line); in atmel_pinctrl_probe()
1132 group->name = group_names[i] = pin_desc[i].name; in atmel_pinctrl_probe()
1133 group->pin = pin_desc[i].number; in atmel_pinctrl_probe()
1135 dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line); in atmel_pinctrl_probe()
1138 atmel_pioctrl->gpio_chip = &atmel_gpio_chip; in atmel_pinctrl_probe()
1139 atmel_pioctrl->gpio_chip->of_node = dev->of_node; in atmel_pinctrl_probe()
1140 atmel_pioctrl->gpio_chip->ngpio = atmel_pioctrl->npins; in atmel_pinctrl_probe()
1141 atmel_pioctrl->gpio_chip->label = dev_name(dev); in atmel_pinctrl_probe()
1142 atmel_pioctrl->gpio_chip->parent = dev; in atmel_pinctrl_probe()
1143 atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names; in atmel_pinctrl_probe()
1145 atmel_pioctrl->pm_wakeup_sources = devm_kcalloc(dev, in atmel_pinctrl_probe()
1146 atmel_pioctrl->nbanks, in atmel_pinctrl_probe()
1147 sizeof(*atmel_pioctrl->pm_wakeup_sources), in atmel_pinctrl_probe()
1149 if (!atmel_pioctrl->pm_wakeup_sources) in atmel_pinctrl_probe()
1150 return -ENOMEM; in atmel_pinctrl_probe()
1152 atmel_pioctrl->pm_suspend_backup = devm_kcalloc(dev, in atmel_pinctrl_probe()
1153 atmel_pioctrl->nbanks, in atmel_pinctrl_probe()
1154 sizeof(*atmel_pioctrl->pm_suspend_backup), in atmel_pinctrl_probe()
1156 if (!atmel_pioctrl->pm_suspend_backup) in atmel_pinctrl_probe()
1157 return -ENOMEM; in atmel_pinctrl_probe()
1159 atmel_pioctrl->irqs = devm_kcalloc(dev, in atmel_pinctrl_probe()
1160 atmel_pioctrl->nbanks, in atmel_pinctrl_probe()
1161 sizeof(*atmel_pioctrl->irqs), in atmel_pinctrl_probe()
1163 if (!atmel_pioctrl->irqs) in atmel_pinctrl_probe()
1164 return -ENOMEM; in atmel_pinctrl_probe()
1166 /* There is one controller but each bank has its own irq line. */ in atmel_pinctrl_probe()
1167 for (i = 0; i < atmel_pioctrl->nbanks; i++) { in atmel_pinctrl_probe()
1172 return -EINVAL; in atmel_pinctrl_probe()
1174 atmel_pioctrl->irqs[i] = res->start; in atmel_pinctrl_probe()
1175 irq_set_chained_handler_and_data(res->start, in atmel_pinctrl_probe()
1177 dev_dbg(dev, "bank %i: irq=%pr\n", i, res); in atmel_pinctrl_probe()
1180 atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node, in atmel_pinctrl_probe()
1181 atmel_pioctrl->gpio_chip->ngpio, in atmel_pinctrl_probe()
1183 if (!atmel_pioctrl->irq_domain) { in atmel_pinctrl_probe()
1185 return -ENODEV; in atmel_pinctrl_probe()
1187 atmel_pioctrl->irq_domain->name = "atmel gpio"; in atmel_pinctrl_probe()
1189 for (i = 0; i < atmel_pioctrl->npins; i++) { in atmel_pinctrl_probe()
1190 int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i); in atmel_pinctrl_probe()
1200 ret = clk_prepare_enable(atmel_pioctrl->clk); in atmel_pinctrl_probe()
1206 atmel_pioctrl->pinctrl_dev = devm_pinctrl_register(&pdev->dev, in atmel_pinctrl_probe()
1209 if (IS_ERR(atmel_pioctrl->pinctrl_dev)) { in atmel_pinctrl_probe()
1210 ret = PTR_ERR(atmel_pioctrl->pinctrl_dev); in atmel_pinctrl_probe()
1215 ret = gpiochip_add_data(atmel_pioctrl->gpio_chip, atmel_pioctrl); in atmel_pinctrl_probe()
1221 ret = gpiochip_add_pin_range(atmel_pioctrl->gpio_chip, dev_name(dev), in atmel_pinctrl_probe()
1222 0, 0, atmel_pioctrl->gpio_chip->ngpio); in atmel_pinctrl_probe()
1228 dev_info(&pdev->dev, "atmel pinctrl initialized\n"); in atmel_pinctrl_probe()
1233 gpiochip_remove(atmel_pioctrl->gpio_chip); in atmel_pinctrl_probe()
1236 clk_disable_unprepare(atmel_pioctrl->clk); in atmel_pinctrl_probe()
1239 irq_domain_remove(atmel_pioctrl->irq_domain); in atmel_pinctrl_probe()
1246 .name = "pinctrl-at91-pio4",