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/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dintel,keembay-phy-usb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/intel,keembay-phy-usb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
14 const: intel,keembay-usb-phy
18 - description: USB APB CPR (clock, power, reset) register
19 - description: USB APB slave register
21 reg-names:
23 - const: cpr-apb-base
[all …]
/Linux-v6.1/drivers/clocksource/
Ddw_apb_timer.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Support for the Synopsys DesignWare APB Timers.
51 return readl(timer->base + offs); in apbt_readl()
57 writel(val, timer->base + offs); in apbt_writel()
62 return readl_relaxed(timer->base + offs); in apbt_readl_relaxed()
68 writel_relaxed(val, timer->base + offs); in apbt_writel_relaxed()
80 * dw_apb_clockevent_pause() - stop the clock_event_device from running
82 * @dw_ced: The APB clock to stop generating events.
86 disable_irq(dw_ced->timer.irq); in dw_apb_clockevent_pause()
87 apbt_disable_int(&dw_ced->timer); in dw_apb_clockevent_pause()
[all …]
Ddw_apb_timer_of.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Modified from mach-picoxcell/time.c
18 void __iomem **base, u32 *rate) in timer_get_base_and_rate() argument
25 *base = of_iomap(np, 0); in timer_get_base_and_rate()
27 if (!*base) in timer_get_base_and_rate()
50 if (!of_property_read_u32(np, "clock-freq", rate) || in timer_get_base_and_rate()
51 !of_property_read_u32(np, "clock-frequency", rate)) in timer_get_base_and_rate()
66 ret = -EINVAL; in timer_get_base_and_rate()
81 iounmap(*base); in timer_get_base_and_rate()
100 ced = dw_apb_clockevent_init(-1, event_timer->name, 300, iobase, irq, in add_clockevent()
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/Linux-v6.1/Documentation/devicetree/bindings/memory-controllers/
Dmediatek,smi-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Yong Wu <yong.wu@mediatek.com>
22 register which control the iommu port is at each larb's register base. But
23 for generation 1, the register is at smi ao base(smi always on register
24 base). Besides that, the smi async clock should be prepared and enabled for
31 - enum:
32 - mediatek,mt2701-smi-common
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/Linux-v6.1/drivers/phy/hisilicon/
Dphy-hi3670-pcie.c1 // SPDX-License-Identifier: GPL-2.0
154 void __iomem *base; member
155 struct regmap *apb; member
171 writel(val, phy->base + APB_PHY_START_ADDR + reg); in hi3670_apb_phy_writel()
176 return readl(phy->base + APB_PHY_START_ADDR + reg); in hi3670_apb_phy_readl()
193 writel(val, phy->base + reg); in kirin_apb_natural_phy_writel()
199 return readl(phy->base + reg); in kirin_apb_natural_phy_readl()
206 regmap_read(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, &val); in hi3670_pcie_phy_oe_enable()
212 regmap_write(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, val); in hi3670_pcie_phy_oe_enable()
217 struct device *dev = phy->dev; in hi3670_pcie_get_eyeparam()
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/Linux-v6.1/Documentation/devicetree/bindings/clock/
Dlpc1850-cgu.txt5 a base clock and itself is one of the inputs to the two Clock
13 corresponds to one of the base clocks for the LPC18xx.
15 - Above text taken from NXP LPC1850 User Manual.
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
22 - compatible:
23 Should be "nxp,lpc1850-cgu"
24 - reg:
25 Shall define the base and range of the address space
27 - #clock-cells:
28 Shall have value <1>. The permitted clock-specifier values
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/Linux-v6.1/drivers/pci/controller/dwc/
Dpcie-kirin.c1 // SPDX-License-Identifier: GPL-2.0
30 #include "pcie-designware.h"
32 #define to_kirin_pcie(x) dev_get_drvdata((x)->dev)
39 /* info located in APB */
61 * in-board Ethernet adapter and the other two connected to M.2 and mini
77 struct regmap *apb; member
84 /* Per-slot PERST# */
89 /* Per-slot clkreq */
102 /* PHY info located in APB */
129 void __iomem *base; member
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/Linux-v6.1/drivers/clk/sprd/
Dsc9860-clk.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/sprd,sc9860-clk.h>
25 static CLK_FIXED_FACTOR(fac_4m, "fac-4m", "ext-26m",
27 static CLK_FIXED_FACTOR(fac_2m, "fac-2m", "ext-26m",
29 static CLK_FIXED_FACTOR(fac_1m, "fac-1m", "ext-26m",
31 static CLK_FIXED_FACTOR(fac_250k, "fac-250k", "ext-26m",
33 static CLK_FIXED_FACTOR(fac_rpll0_26m, "rpll0-26m", "ext-26m",
35 static CLK_FIXED_FACTOR(fac_rpll1_26m, "rpll1-26m", "ext-26m",
37 static CLK_FIXED_FACTOR(fac_rco_25m, "rco-25m", "ext-rc0-100m",
[all …]
/Linux-v6.1/drivers/clk/mmp/
Dclk-apbc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * mmp APB clock operation source file
17 /* Common APB clock register bit definitions */
18 #define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */
26 void __iomem *base; member
42 if (apbc->lock) in clk_apbc_prepare()
43 spin_lock_irqsave(apbc->lock, flags); in clk_apbc_prepare()
45 data = readl_relaxed(apbc->base); in clk_apbc_prepare()
46 if (apbc->flags & APBC_POWER_CTRL) in clk_apbc_prepare()
49 writel_relaxed(data, apbc->base); in clk_apbc_prepare()
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/Linux-v6.1/Documentation/devicetree/bindings/interrupt-controller/
Dsnps,dw-apb-ictl.txt1 Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
3 Synopsys DesignWare provides interrupt controller IP for APB known as
5 APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt
9 - compatible: shall be "snps,dw-apb-ictl"
10 - reg: physical base address of the controller and length of memory mapped
12 - interrupt-controller: identifies the node as an interrupt controller
13 - #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
16 - interrupts: interrupt reference to primary interrupt controller
20 - 0 maps to bit 0 of low interrupts,
21 - 1 maps to bit 1 of low interrupts,
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/Linux-v6.1/arch/arc/boot/dts/
Daxc001.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "simple-bus";
20 #address-cells = <1>;
21 #size-cells = <1>;
26 #clock-cells = <0>;
27 compatible = "fixed-clock";
28 clock-frequency = <750000000>;
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/Linux-v6.1/Documentation/devicetree/bindings/display/imx/
Dnxp,imx8mq-dcss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Laurentiu Palcu <laurentiu.palcu@nxp.com>
17 2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
23 const: nxp,imx8mq-dcss
27 - description: DCSS base address and size, up to IRQ steer start
28 - description: DCSS BLKCTL base address and size
32 - description: Context loader completion and error interrupt
[all …]
/Linux-v6.1/drivers/gpu/drm/bridge/imx/
Dimx8qxp-pixel-combiner.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <linux/media-bus-format.h>
52 #define DRIVER_NAME "imx8qxp-pixel-combiner"
73 void __iomem *base; member
78 return readl(pc->base + offset); in imx8qxp_pc_read()
84 writel(value, pc->base + offset); in imx8qxp_pc_write()
104 if (mode->hdisplay > 2560) in imx8qxp_pc_bridge_mode_valid()
113 struct imx8qxp_pc_channel *ch = bridge->driver_private; in imx8qxp_pc_bridge_attach()
114 struct imx8qxp_pc *pc = ch->pc; in imx8qxp_pc_bridge_attach()
117 DRM_DEV_ERROR(pc->dev, in imx8qxp_pc_bridge_attach()
[all …]
/Linux-v6.1/drivers/phy/intel/
Dphy-intel-keembay-usb.c1 // SPDX-License-Identifier: GPL-2.0-only
35 /* USS APB slave registers */
76 ret = regmap_update_bits(priv->regmap_cpr, USS_CPR_CLK_SET, in keembay_usb_clocks_on()
79 dev_err(priv->dev, "error clock set: %d\n", ret); in keembay_usb_clocks_on()
83 ret = regmap_update_bits(priv->regmap_cpr, USS_CPR_RST_SET, in keembay_usb_clocks_on()
86 dev_err(priv->dev, "error reset set: %d\n", ret); in keembay_usb_clocks_on()
90 ret = regmap_update_bits(priv->regmap_slv, in keembay_usb_clocks_on()
95 dev_err(priv->dev, "error iddq disable: %d\n", ret); in keembay_usb_clocks_on()
102 ret = regmap_update_bits(priv->regmap_slv, USS_USB_PHY_CFG0, in keembay_usb_clocks_on()
106 dev_err(priv->dev, "error ref clock select: %d\n", ret); in keembay_usb_clocks_on()
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/pci/
Drockchip-pcie-ep.txt4 - compatible: Should contain "rockchip,rk3399-pcie-ep"
5 - reg: Two register ranges as listed in the reg-names property
6 - reg-names: Must include the following names
7 - "apb-base"
8 - "mem-base"
9 - clocks: Must contain an entry for each entry in clock-names.
10 See ../clocks/clock-bindings.txt for details.
11 - clock-names: Must include the following entries:
12 - "aclk"
13 - "aclk-perf"
[all …]
Drcar-pci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Renesas Electronics Europe GmbH - https://www.renesas.com/eu/en/
4 ---
5 $id: http://devicetree.org/schemas/pci/rcar-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car PCIe Endpoint
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
12 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
17 - enum:
18 - renesas,r8a774a1-pcie-ep # RZ/G2M
[all …]
Drockchip-pcie-host.txt4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
14 See ../clocks/clock-bindings.txt for details.
[all …]
/Linux-v6.1/arch/arc/plat-axs10x/
Daxs10x.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
12 #include <asm/asm-offsets.h>
32 * intermediate DW APB GPIO blocks (mainly for debouncing) in axs10x_enable_gpio_intc_wire()
34 * --------------------- in axs10x_enable_gpio_intc_wire()
35 * | snps,arc700-intc | in axs10x_enable_gpio_intc_wire()
36 * --------------------- in axs10x_enable_gpio_intc_wire()
38 * ------------------- ------------------- in axs10x_enable_gpio_intc_wire()
39 * | snps,dw-apb-gpio | | snps,dw-apb-gpio | in axs10x_enable_gpio_intc_wire()
40 * ------------------- ------------------- in axs10x_enable_gpio_intc_wire()
[all …]
/Linux-v6.1/drivers/soc/imx/
Dimx8mp-blk-ctrl.c1 // SPDX-License-Identifier: GPL-2.0+
17 #include <dt-bindings/power/imx8mp-power.h>
79 switch (domain->id) { in imx8mp_hsio_blk_ctrl_power_on()
81 regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN); in imx8mp_hsio_blk_ctrl_power_on()
84 regmap_set_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN); in imx8mp_hsio_blk_ctrl_power_on()
87 regmap_set_bits(bc->regmap, GPR_REG0, in imx8mp_hsio_blk_ctrl_power_on()
98 switch (domain->id) { in imx8mp_hsio_blk_ctrl_power_off()
100 regmap_clear_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN); in imx8mp_hsio_blk_ctrl_power_off()
103 regmap_clear_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN); in imx8mp_hsio_blk_ctrl_power_off()
106 regmap_clear_bits(bc->regmap, GPR_REG0, in imx8mp_hsio_blk_ctrl_power_off()
[all …]
Dimx8m-blk-ctrl.c1 // SPDX-License-Identifier: GPL-2.0+
17 #include <dt-bindings/power/imx8mm-power.h>
18 #include <dt-bindings/power/imx8mn-power.h>
19 #include <dt-bindings/power/imx8mp-power.h>
20 #include <dt-bindings/power/imx8mq-power.h>
51 * an if-statement should be used before setting and clearing this
86 const struct imx8m_blk_ctrl_domain_data *data = domain->data; in imx8m_blk_ctrl_power_on()
87 struct imx8m_blk_ctrl *bc = domain->bc; in imx8m_blk_ctrl_power_on()
91 ret = pm_runtime_get_sync(bc->bus_power_dev); in imx8m_blk_ctrl_power_on()
93 pm_runtime_put_noidle(bc->bus_power_dev); in imx8m_blk_ctrl_power_on()
[all …]
/Linux-v6.1/drivers/clk/sunxi-ng/
Dccu-suniv-f1c100s.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
25 #include "ccu-suniv-f1c100s.h"
39 .hw.init = CLK_HW_INIT("pll-cpu", "osc24M",
47 * the base (2x, 4x and 8x), and one variable divider (the one true
55 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
63 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
75 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
87 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr",
103 .hw.init = CLK_HW_INIT("pll-periph", "osc24M",
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/memory-controllers/fsl/
Dimx8m-ddrc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peng Fan <peng.fan@nxp.com>
18 switching is implemented by TF-A code which runs from a SRAM area.
27 - enum:
28 - fsl,imx8mn-ddrc
29 - fsl,imx8mm-ddrc
30 - fsl,imx8mq-ddrc
[all …]
/Linux-v6.1/drivers/clk/
Dclk-gemini.c1 // SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "clk-gemini: " fmt
15 #include <linux/clk-provider.h>
21 #include <linux/reset-controller.h>
22 #include <dt-bindings/reset/cortina,gemini-reset.h>
23 #include <dt-bindings/clock/cortina,gemini-clock.h>
53 * struct gemini_gate_data - Gemini gated clocks
67 * struct clk_gemini_pci - Gemini PCI clock
79 * struct gemini_reset - gemini reset controller
92 { 1, "security-gate", "secdiv", 0 },
[all …]
/Linux-v6.1/drivers/media/rc/
Dsunxi-cir.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2014 Alexsey Shestacov <wingrime@linux-sunxi.org>
8 * Based on sun5i-ir.c:
9 * Copyright (C) 2007-2012 Daniel Wang
18 #include <media/rc-core.h>
20 #define SUNXI_IR_DEV "sunxi-ir"
61 #define REG_RXSTA_GET_AC(val) (((val) >> 8) & (ir->fifo_size * 2 - 1))
78 * struct sunxi_ir_quirks - Differences between SoC variants.
90 void __iomem *base; member
107 status = readl(ir->base + SUNXI_IR_RXSTA_REG); in sunxi_ir_irq()
[all …]
/Linux-v6.1/include/linux/
Ddw_apb_timer.h1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * Support for the Synopsys DesignWare APB Timers.
20 void __iomem *base; member
43 void __iomem *base, int irq, unsigned long freq);
45 dw_apb_clocksource_init(unsigned rating, const char *name, void __iomem *base,

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