Searched +full:adrst +full:- +full:n (Results 1 – 5 of 5) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/iio/adc/renesas,rzg2l-adc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>13 A/D Converter block is a successive approximation analog-to-digital converter14 with a 12-bit accuracy. Up to eight analog input channels can be selected.16 stored in a 32-bit data register corresponding to each channel.21 - enum:22 - renesas,r9a07g043-adc # RZ/G2UL[all …]
1 // SPDX-License-Identifier: GPL-2.07 * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>24 #define DRIVER_NAME "rzg2l-adc"26 #define RZG2L_ADM(n) ((n) * 0x4) argument56 #define RZG2L_ADCR(n) (0x30 + ((n) * 0x4)) argument95 return readl(adc->base + reg); in rzg2l_adc_readl()100 writel(val, adc->base + reg); in rzg2l_adc_writel()134 timeout--; in rzg2l_adc_start_stop()136 pr_err("%s stopping ADC timed out\n", __func__); in rzg2l_adc_start_stop()148 * EGA[13:12] - Set 00 to indicate hardware trigger is invalid in rzg2l_set_trigger()[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)8 #include <dt-bindings/interrupt-controller/arm-gic.h>9 #include <dt-bindings/clock/r9a07g043-cpg.h>13 #address-cells = <2>;14 #size-cells = <2>;16 audio_clk1: audio1-clk {17 compatible = "fixed-clock";18 #clock-cells = <0>;20 clock-frequency = <0>;23 audio_clk2: audio2-clk {[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)8 #include <dt-bindings/interrupt-controller/arm-gic.h>9 #include <dt-bindings/clock/r9a07g054-cpg.h>13 #address-cells = <2>;14 #size-cells = <2>;16 audio_clk1: audio1-clk {17 compatible = "fixed-clock";18 #clock-cells = <0>;20 clock-frequency = <0>;23 audio_clk2: audio2-clk {[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)8 #include <dt-bindings/interrupt-controller/arm-gic.h>9 #include <dt-bindings/clock/r9a07g044-cpg.h>13 #address-cells = <2>;14 #size-cells = <2>;16 audio_clk1: audio1-clk {17 compatible = "fixed-clock";18 #clock-cells = <0>;20 clock-frequency = <0>;23 audio_clk2: audio2-clk {[all …]
