Lines Matching +full:adrst +full:- +full:n
1 // SPDX-License-Identifier: GPL-2.0
7 * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
24 #define DRIVER_NAME "rzg2l-adc"
26 #define RZG2L_ADM(n) ((n) * 0x4) argument
56 #define RZG2L_ADCR(n) (0x30 + ((n) * 0x4)) argument
95 return readl(adc->base + reg); in rzg2l_adc_readl()
100 writel(val, adc->base + reg); in rzg2l_adc_writel()
134 timeout--; in rzg2l_adc_start_stop()
136 pr_err("%s stopping ADC timed out\n", __func__); in rzg2l_adc_start_stop()
148 * EGA[13:12] - Set 00 to indicate hardware trigger is invalid in rzg2l_set_trigger()
149 * BS[4] - Enable 1-buffer mode in rzg2l_set_trigger()
150 * MS[1] - Enable Select mode in rzg2l_set_trigger()
151 * TRG[0] - Enable software trigger mode in rzg2l_set_trigger()
166 return -EBUSY; in rzg2l_adc_conversion_setup()
178 * INTS[31] - Select pulse signal in rzg2l_adc_conversion_setup()
179 * CSEEN[16] - Enable channel select error interrupt in rzg2l_adc_conversion_setup()
180 * INTEN[7:0] - Select channel interrupt in rzg2l_adc_conversion_setup()
193 struct device *dev = indio_dev->dev.parent; in rzg2l_adc_set_power()
215 reinit_completion(&adc->completion); in rzg2l_adc_conversion()
219 if (!wait_for_completion_timeout(&adc->completion, RZG2L_ADC_TIMEOUT)) { in rzg2l_adc_conversion()
224 return -ETIMEDOUT; in rzg2l_adc_conversion()
240 if (chan->type != IIO_VOLTAGE) in rzg2l_adc_read_raw()
241 return -EINVAL; in rzg2l_adc_read_raw()
243 mutex_lock(&adc->lock); in rzg2l_adc_read_raw()
244 ch = chan->channel & RZG2L_ADC_CHN_MASK; in rzg2l_adc_read_raw()
247 mutex_unlock(&adc->lock); in rzg2l_adc_read_raw()
250 *val = adc->last_val[ch]; in rzg2l_adc_read_raw()
251 mutex_unlock(&adc->lock); in rzg2l_adc_read_raw()
256 return -EINVAL; in rzg2l_adc_read_raw()
264 return sysfs_emit(label, "%s\n", rzg2l_adc_channel_name[chan->channel]); in rzg2l_adc_read_label()
292 adc->last_val[ch] = rzg2l_adc_readl(adc, RZG2L_ADCR(ch)) & RZG2L_ADCR_AD_MASK; in rzg2l_adc_isr()
297 complete(&adc->completion); in rzg2l_adc_isr()
312 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); in rzg2l_adc_parse_properties()
314 return -ENOMEM; in rzg2l_adc_parse_properties()
316 num_channels = device_get_child_node_count(&pdev->dev); in rzg2l_adc_parse_properties()
318 dev_err(&pdev->dev, "no channel children\n"); in rzg2l_adc_parse_properties()
319 return -ENODEV; in rzg2l_adc_parse_properties()
323 dev_err(&pdev->dev, "num of channel children out of range\n"); in rzg2l_adc_parse_properties()
324 return -EINVAL; in rzg2l_adc_parse_properties()
327 chan_array = devm_kcalloc(&pdev->dev, num_channels, sizeof(*chan_array), in rzg2l_adc_parse_properties()
330 return -ENOMEM; in rzg2l_adc_parse_properties()
333 device_for_each_child_node(&pdev->dev, fwnode) { in rzg2l_adc_parse_properties()
342 return -EINVAL; in rzg2l_adc_parse_properties()
353 data->num_channels = num_channels; in rzg2l_adc_parse_properties()
354 data->channels = chan_array; in rzg2l_adc_parse_properties()
355 adc->data = data; in rzg2l_adc_parse_properties()
366 ret = clk_prepare_enable(adc->pclk); in rzg2l_adc_hw_init()
377 ret = -EBUSY; in rzg2l_adc_hw_init()
380 timeout--; in rzg2l_adc_hw_init()
392 * ADIL[31:24] - Should be always set to 0 in rzg2l_adc_hw_init()
393 * ADCMP[23:16] - Should be always set to 0xe in rzg2l_adc_hw_init()
394 * ADSMP[15:0] - Set default (0x578) sampling period in rzg2l_adc_hw_init()
404 clk_disable_unprepare(adc->pclk); in rzg2l_adc_hw_init()
413 pm_runtime_disable(dev->parent); in rzg2l_adc_pm_runtime_disable()
420 pm_runtime_set_suspended(dev->parent); in rzg2l_adc_pm_runtime_set_suspended()
430 struct device *dev = &pdev->dev; in rzg2l_adc_probe()
438 return -ENOMEM; in rzg2l_adc_probe()
446 mutex_init(&adc->lock); in rzg2l_adc_probe()
448 adc->base = devm_platform_ioremap_resource(pdev, 0); in rzg2l_adc_probe()
449 if (IS_ERR(adc->base)) in rzg2l_adc_probe()
450 return PTR_ERR(adc->base); in rzg2l_adc_probe()
452 adc->pclk = devm_clk_get(dev, "pclk"); in rzg2l_adc_probe()
453 if (IS_ERR(adc->pclk)) { in rzg2l_adc_probe()
455 return PTR_ERR(adc->pclk); in rzg2l_adc_probe()
458 adc->adclk = devm_clk_get(dev, "adclk"); in rzg2l_adc_probe()
459 if (IS_ERR(adc->adclk)) { in rzg2l_adc_probe()
461 return PTR_ERR(adc->adclk); in rzg2l_adc_probe()
464 adc->adrstn = devm_reset_control_get_exclusive(dev, "adrst-n"); in rzg2l_adc_probe()
465 if (IS_ERR(adc->adrstn)) { in rzg2l_adc_probe()
466 dev_err(dev, "failed to get adrstn\n"); in rzg2l_adc_probe()
467 return PTR_ERR(adc->adrstn); in rzg2l_adc_probe()
470 adc->presetn = devm_reset_control_get_exclusive(dev, "presetn"); in rzg2l_adc_probe()
471 if (IS_ERR(adc->presetn)) { in rzg2l_adc_probe()
472 dev_err(dev, "failed to get presetn\n"); in rzg2l_adc_probe()
473 return PTR_ERR(adc->presetn); in rzg2l_adc_probe()
476 ret = reset_control_deassert(adc->adrstn); in rzg2l_adc_probe()
478 dev_err(&pdev->dev, "failed to deassert adrstn pin, %d\n", ret); in rzg2l_adc_probe()
482 ret = devm_add_action_or_reset(&pdev->dev, in rzg2l_adc_probe()
483 rzg2l_adc_reset_assert, adc->adrstn); in rzg2l_adc_probe()
485 dev_err(&pdev->dev, "failed to register adrstn assert devm action, %d\n", in rzg2l_adc_probe()
490 ret = reset_control_deassert(adc->presetn); in rzg2l_adc_probe()
492 dev_err(&pdev->dev, "failed to deassert presetn pin, %d\n", ret); in rzg2l_adc_probe()
496 ret = devm_add_action_or_reset(&pdev->dev, in rzg2l_adc_probe()
497 rzg2l_adc_reset_assert, adc->presetn); in rzg2l_adc_probe()
499 dev_err(&pdev->dev, "failed to register presetn assert devm action, %d\n", in rzg2l_adc_probe()
506 dev_err(&pdev->dev, "failed to initialize ADC HW, %d\n", ret); in rzg2l_adc_probe()
519 init_completion(&adc->completion); in rzg2l_adc_probe()
523 indio_dev->name = DRIVER_NAME; in rzg2l_adc_probe()
524 indio_dev->info = &rzg2l_adc_iio_info; in rzg2l_adc_probe()
525 indio_dev->modes = INDIO_DIRECT_MODE; in rzg2l_adc_probe()
526 indio_dev->channels = adc->data->channels; in rzg2l_adc_probe()
527 indio_dev->num_channels = adc->data->num_channels; in rzg2l_adc_probe()
530 ret = devm_add_action_or_reset(&pdev->dev, in rzg2l_adc_probe()
531 rzg2l_adc_pm_runtime_set_suspended, &indio_dev->dev); in rzg2l_adc_probe()
536 ret = devm_add_action_or_reset(&pdev->dev, in rzg2l_adc_probe()
537 rzg2l_adc_pm_runtime_disable, &indio_dev->dev); in rzg2l_adc_probe()
545 { .compatible = "renesas,rzg2l-adc",},
556 clk_disable_unprepare(adc->adclk); in rzg2l_adc_pm_runtime_suspend()
557 clk_disable_unprepare(adc->pclk); in rzg2l_adc_pm_runtime_suspend()
568 ret = clk_prepare_enable(adc->pclk); in rzg2l_adc_pm_runtime_resume()
572 ret = clk_prepare_enable(adc->adclk); in rzg2l_adc_pm_runtime_resume()
574 clk_disable_unprepare(adc->pclk); in rzg2l_adc_pm_runtime_resume()
600 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");