| /Linux-v5.15/drivers/iommu/arm/arm-smmu/ |
| D | arm-smmu.c | 3 * IOMMU API for ARM architected SMMU implementations.
13 * - Non-secure access to the SMMU
18 #define pr_fmt(fmt) "arm-smmu: " fmt
43 #include "arm-smmu.h"
46 * Apparently, some Qualcomm arm64 platforms which appear to expose their SMMU
60 …"Force SMMU mappings to be installed at a particular stage of translation. A value of '1' or '2' f…
65 …domain will report an abort back to the device and will not be allowed to pass through the SMMU.");
73 static inline int arm_smmu_rpm_get(struct arm_smmu_device *smmu) in arm_smmu_rpm_get() argument
75 if (pm_runtime_enabled(smmu->dev)) in arm_smmu_rpm_get()
76 return pm_runtime_resume_and_get(smmu->dev); in arm_smmu_rpm_get()
[all …]
|
| D | arm-smmu-qcom.c | 7 #include <linux/adreno-smmu-priv.h>
11 #include "arm-smmu.h"
14 struct arm_smmu_device smmu; member
20 static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) in to_qcom_smmu() argument
22 return container_of(smmu, struct qcom_smmu, smmu); in to_qcom_smmu()
25 static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx, in qcom_adreno_smmu_write_sctlr() argument
28 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); in qcom_adreno_smmu_write_sctlr()
39 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); in qcom_adreno_smmu_write_sctlr()
47 struct arm_smmu_device *smmu = smmu_domain->smmu; in qcom_adreno_smmu_get_fault_info() local
49 info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR); in qcom_adreno_smmu_get_fault_info()
[all …]
|
| D | arm-smmu-impl.c | 2 // Miscellaneous Arm SMMU implementation and integration quirks
5 #define pr_fmt(fmt) "arm-smmu: " fmt
10 #include "arm-smmu.h"
28 static u32 arm_smmu_read_ns(struct arm_smmu_device *smmu, int page, in arm_smmu_read_ns() argument
33 return readl_relaxed(arm_smmu_page(smmu, page) + offset); in arm_smmu_read_ns()
36 static void arm_smmu_write_ns(struct arm_smmu_device *smmu, int page, in arm_smmu_write_ns() argument
41 writel_relaxed(val, arm_smmu_page(smmu, page) + offset); in arm_smmu_write_ns()
52 struct arm_smmu_device smmu; member
56 static int cavium_cfg_probe(struct arm_smmu_device *smmu) in cavium_cfg_probe() argument
59 struct cavium_smmu *cs = container_of(smmu, struct cavium_smmu, smmu); in cavium_cfg_probe()
[all …]
|
| D | arm-smmu-nvidia.c | 12 #include "arm-smmu.h"
21 * In addition, the SMMU driver needs to coordinate with the memory controller
30 * SMMU instance.
35 struct arm_smmu_device smmu; member
41 static inline struct nvidia_smmu *to_nvidia_smmu(struct arm_smmu_device *smmu) in to_nvidia_smmu() argument
43 return container_of(smmu, struct nvidia_smmu, smmu); in to_nvidia_smmu()
46 static inline void __iomem *nvidia_smmu_page(struct arm_smmu_device *smmu, in nvidia_smmu_page() argument
51 nvidia_smmu = container_of(smmu, struct nvidia_smmu, smmu); in nvidia_smmu_page()
52 return nvidia_smmu->bases[inst] + (page << smmu->pgshift); in nvidia_smmu_page()
55 static u32 nvidia_smmu_read_reg(struct arm_smmu_device *smmu, in nvidia_smmu_read_reg() argument
[all …]
|
| D | arm-smmu.h | 3 * IOMMU API for ARM architected SMMU implementations.
242 /* Maximum number of context banks per SMMU */
368 struct arm_smmu_device *smmu; member
374 struct mutex init_mutex; /* Protects smmu pointer */
380 struct arm_smmu_device *smmu; member
425 u32 (*read_reg)(struct arm_smmu_device *smmu, int page, int offset);
426 void (*write_reg)(struct arm_smmu_device *smmu, int page, int offset,
428 u64 (*read_reg64)(struct arm_smmu_device *smmu, int page, int offset);
429 void (*write_reg64)(struct arm_smmu_device *smmu, int page, int offset,
431 int (*cfg_probe)(struct arm_smmu_device *smmu);
[all …]
|
| D | Makefile | 4 arm_smmu-objs += arm-smmu.o arm-smmu-impl.o arm-smmu-nvidia.o
5 arm_smmu-$(CONFIG_ARM_SMMU_QCOM) += arm-smmu-qcom.o
|
| /Linux-v5.15/drivers/iommu/ |
| D | tegra-smmu.c | 24 struct tegra_smmu *smmu; member
54 struct tegra_smmu *smmu; member
70 static inline void smmu_writel(struct tegra_smmu *smmu, u32 value, in smmu_writel() argument
73 writel(value, smmu->regs + offset); in smmu_writel()
76 static inline u32 smmu_readl(struct tegra_smmu *smmu, unsigned long offset) in smmu_readl() argument
78 return readl(smmu->regs + offset); in smmu_readl()
87 #define SMMU_TLB_CONFIG_ACTIVE_LINES(smmu) \ argument
88 ((smmu)->soc->num_tlb_lines & (smmu)->tlb_mask)
166 static bool smmu_dma_addr_valid(struct tegra_smmu *smmu, dma_addr_t addr) in smmu_dma_addr_valid() argument
169 return (addr & smmu->pfn_mask) == addr; in smmu_dma_addr_valid()
[all …]
|
| D | Kconfig | 241 bool "NVIDIA Tegra SMMU Support"
247 This driver supports the IOMMU hardware (SMMU) found on NVIDIA Tegra
309 tristate "ARM Ltd. System MMU (SMMU) Support"
319 the ARM SMMU architecture.
327 to the SMMU but does not provide any support via the DMA API.
334 bool "Default to disabling bypass on ARM SMMU v1 and v2"
341 will not be allowed to pass through the SMMU.
355 'arm-smmu.disable_bypass' will continue to override this
364 of the ARM SMMU, this needs to be built into the SMMU driver.
|
| /Linux-v5.15/drivers/iommu/arm/arm-smmu-v3/ |
| D | arm-smmu-v3.c | 33 #include "arm-smmu-v3.h"
39 …domain will report an abort back to the device and will not be allowed to pass through the SMMU.");
91 static void parse_driver_options(struct arm_smmu_device *smmu) in parse_driver_options() argument
96 if (of_property_read_bool(smmu->dev->of_node, in parse_driver_options()
98 smmu->options |= arm_smmu_options[i].opt; in parse_driver_options()
99 dev_notice(smmu->dev, "option %s\n", in parse_driver_options()
182 static void queue_poll_init(struct arm_smmu_device *smmu, in queue_poll_init() argument
187 qp->wfe = !!(smmu->features & ARM_SMMU_FEAT_SEV); in queue_poll_init()
338 static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu) in arm_smmu_get_cmdq() argument
340 return &smmu->cmdq; in arm_smmu_get_cmdq()
[all …]
|
| D | arm-smmu-v3-sva.c | 11 #include "arm-smmu-v3.h"
40 * Check if the CPU ASID is available on the SMMU side. If a private context
49 struct arm_smmu_device *smmu; in arm_smmu_share_asid() local
65 smmu = smmu_domain->smmu; in arm_smmu_share_asid()
68 XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL); in arm_smmu_share_asid()
85 arm_smmu_tlb_inv_asid(smmu, asid); in arm_smmu_share_asid()
188 if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_BTM)) in arm_smmu_mm_invalidate_range()
211 arm_smmu_tlb_inv_asid(smmu_domain->smmu, smmu_mn->cd->asid); in arm_smmu_mm_release()
298 arm_smmu_tlb_inv_asid(smmu_domain->smmu, cd->asid); in arm_smmu_mmu_notifier_put()
393 bool arm_smmu_sva_supported(struct arm_smmu_device *smmu) in arm_smmu_sva_supported() argument
[all …]
|
| /Linux-v5.15/Documentation/devicetree/bindings/iommu/ |
| D | arm,smmu.yaml | 4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
18 The SMMU may also raise interrupts in response to various fault
26 - description: Qcom SoCs implementing "arm,smmu-v2"
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
31 - const: qcom,smmu-v2
36 - qcom,sc7180-smmu-500
37 - qcom,sc7280-smmu-500
38 - qcom,sc8180x-smmu-500
39 - qcom,sdm845-smmu-500
[all …]
|
| D | nvidia,tegra30-smmu.txt | 1 NVIDIA Tegra 30 IOMMU H/W, SMMU (System Memory Management Unit)
4 - compatible : "nvidia,tegra30-smmu"
6 of the SMMU register blocks.
10 - nvidia,ahb : phandle to the ahb bus connected to SMMU.
13 smmu {
14 compatible = "nvidia,tegra30-smmu";
|
| D | arm,smmu-v3.yaml | 4 $id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
23 const: arm,smmu-v3
52 Present if page table walks made by the SMMU are cache coherent with the
55 NOTE: this only applies to the SMMU itself, not masters connected
56 upstream of the SMMU.
62 description: Avoid sending CMD_PREFETCH_* commands to the SMMU.
69 doesn't support SMMU page1 register space.
84 compatible = "arm,smmu-v3";
|
| /Linux-v5.15/drivers/memory/tegra/ |
| D | tegra210.c | 20 .smmu = {
36 .smmu = {
52 .smmu = {
68 .smmu = {
84 .smmu = {
100 .smmu = {
116 .smmu = {
132 .smmu = {
148 .smmu = {
164 .smmu = {
[all …]
|
| D | tegra114.c | 31 .smmu = {
47 .smmu = {
63 .smmu = {
79 .smmu = {
95 .smmu = {
111 .smmu = {
127 .smmu = {
143 .smmu = {
159 .smmu = {
175 .smmu = {
[all …]
|
| D | tegra124.c | 32 .smmu = {
48 .smmu = {
64 .smmu = {
80 .smmu = {
96 .smmu = {
112 .smmu = {
128 .smmu = {
144 .smmu = {
160 .smmu = {
176 .smmu = {
[all …]
|
| D | tegra30.c | 54 .smmu = {
71 .smmu = {
88 .smmu = {
105 .smmu = {
122 .smmu = {
139 .smmu = {
156 .smmu = {
173 .smmu = {
190 .smmu = {
207 .smmu = {
[all …]
|
| /Linux-v5.15/drivers/acpi/arm64/ |
| D | iort.c | 407 struct acpi_iort_smmu_v3 *smmu; in iort_get_id_mapping_index() local
419 smmu = (struct acpi_iort_smmu_v3 *)node->node_data; in iort_get_id_mapping_index()
424 if (smmu->event_gsiv && smmu->pri_gsiv && smmu->gerr_gsiv in iort_get_id_mapping_index()
425 && smmu->sync_gsiv) in iort_get_id_mapping_index()
428 if (smmu->id_mapping_index >= node->mapping_count) { in iort_get_id_mapping_index()
434 return smmu->id_mapping_index; in iort_get_id_mapping_index()
527 * as NC (named component) -> SMMU -> ITS. If the type is matched, in iort_node_map_platform_id()
547 * device (such as SMMU, PMCG),its iort node already cached in iort_find_dev_node()
799 struct acpi_iort_smmu_v3 *smmu; in iort_get_msi_resv_iommu() local
801 smmu = (struct acpi_iort_smmu_v3 *)iommu->node_data; in iort_get_msi_resv_iommu()
[all …]
|
| /Linux-v5.15/arch/arm64/boot/dts/marvell/ |
| D | armada-8040.dtsi | 20 <0x0 &smmu 0x480 0x20>,
21 <0x100 &smmu 0x4a0 0x20>,
22 <0x200 &smmu 0x4c0 0x20>;
36 iommus = <&smmu 0x444>;
40 iommus = <&smmu 0x445>;
44 iommus = <&smmu 0x440>;
48 iommus = <&smmu 0x441>;
52 iommus = <&smmu 0x454>;
56 iommus = <&smmu 0x450>;
60 iommus = <&smmu 0x451>;
|
| D | armada-7040.dtsi | 20 <0x0 &smmu 0x480 0x20>,
21 <0x100 &smmu 0x4a0 0x20>,
22 <0x200 &smmu 0x4c0 0x20>;
27 iommus = <&smmu 0x444>;
31 iommus = <&smmu 0x445>;
35 iommus = <&smmu 0x440>;
39 iommus = <&smmu 0x441>;
|
| D | cn9130-crb-A.dts | 22 <0x0 &smmu 0x480 0x20>,
23 <0x100 &smmu 0x4a0 0x20>,
24 <0x200 &smmu 0x4c0 0x20>;
|
| /Linux-v5.15/Documentation/devicetree/bindings/display/ |
| D | arm,komeda.txt | 15 devicetree/bindings/iommu/arm,smmu-v3.txt,
49 iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>,
50 <&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>,
51 <&smmu 8>, <&smmu 9>;
|
| /Linux-v5.15/include/linux/ |
| D | adreno-smmu-priv.h | 38 * struct adreno_smmu_priv - private interface between adreno-smmu and GPU
40 * @cookie: An opque token provided by adreno-smmu and passed
54 * The GPU driver (drm/msm) and adreno-smmu work together for controlling
55 * the GPU's SMMU instance. This is by necessity, as the GPU is directly
56 * updating the SMMU for context switches, while on the other hand we do
57 * not want to duplicate all of the initial setup logic from arm-smmu.
|
| /Linux-v5.15/include/soc/tegra/ |
| D | mc.h | 32 * Tegra SMMU, whereas on Tegra186 and later this is the ID used to override the ARM SMMU
43 /* Tegra SMMU enable (Tegra210 and earlier) */
47 } smmu; member
102 void tegra_smmu_remove(struct tegra_smmu *smmu);
111 static inline void tegra_smmu_remove(struct tegra_smmu *smmu) in tegra_smmu_remove() argument
198 const struct tegra_smmu_soc *smmu; member
212 struct tegra_smmu *smmu; member
|
| /Linux-v5.15/arch/arm64/boot/dts/xilinx/ |
| D | zynqmp.dtsi | 275 iommus = <&smmu 0x14e8>;
288 iommus = <&smmu 0x14e9>;
301 iommus = <&smmu 0x14ea>;
314 iommus = <&smmu 0x14eb>;
327 iommus = <&smmu 0x14ec>;
340 iommus = <&smmu 0x14ed>;
353 iommus = <&smmu 0x14ee>;
366 iommus = <&smmu 0x14ef>;
396 iommus = <&smmu 0x868>;
409 iommus = <&smmu 0x869>;
[all …]
|
