7 #include <linux/adreno-smmu-priv.h>
11 #include "arm-smmu.h"
14 	struct arm_smmu_device smmu;  member
20 static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)  in to_qcom_smmu()  argument
22 	return container_of(smmu, struct qcom_smmu, smmu);  in to_qcom_smmu()
25 static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx,  in qcom_adreno_smmu_write_sctlr()  argument
28 	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);  in qcom_adreno_smmu_write_sctlr()
39 	arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg);  in qcom_adreno_smmu_write_sctlr()
47 	struct arm_smmu_device *smmu = smmu_domain->smmu;  in qcom_adreno_smmu_get_fault_info()  local
49 	info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR);  in qcom_adreno_smmu_get_fault_info()
50 	info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0);  in qcom_adreno_smmu_get_fault_info()
51 	info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1);  in qcom_adreno_smmu_get_fault_info()
52 	info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR);  in qcom_adreno_smmu_get_fault_info()
53 	info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx));  in qcom_adreno_smmu_get_fault_info()
54 	info->ttbr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0);  in qcom_adreno_smmu_get_fault_info()
55 	info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR);  in qcom_adreno_smmu_get_fault_info()
62 	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu_domain->smmu);  in qcom_adreno_smmu_set_stall()
74 	struct arm_smmu_device *smmu = smmu_domain->smmu;  in qcom_adreno_smmu_resume_translation()  local
80 	arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg);  in qcom_adreno_smmu_resume_translation()
125 	struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx];  in qcom_adreno_smmu_set_ttbr0_cfg()
155 	arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx);  in qcom_adreno_smmu_set_ttbr0_cfg()
161 					       struct arm_smmu_device *smmu,  in qcom_adreno_smmu_alloc_context_bank()  argument
175 		count = smmu->num_context_banks;  in qcom_adreno_smmu_alloc_context_bank()
178 	return __arm_smmu_alloc_bitmap(smmu->context_map, start, count);  in qcom_adreno_smmu_alloc_context_bank()
181 static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu)  in qcom_adreno_can_do_ttbr1()  argument
183 	const struct device_node *np = smmu->dev->of_node;  in qcom_adreno_can_do_ttbr1()
185 	if (of_device_is_compatible(np, "qcom,msm8996-smmu-v2"))  in qcom_adreno_can_do_ttbr1()
203 	 * All targets that use the qcom,adreno-smmu compatible string *should*  in qcom_adreno_smmu_init_context()
204 	 * be AARCH64 stage 1 but double check because the arm-smmu code assumes  in qcom_adreno_smmu_init_context()
207 	if (qcom_adreno_can_do_ttbr1(smmu_domain->smmu) &&  in qcom_adreno_smmu_init_context()
248 static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu)  in qcom_smmu_cfg_probe()  argument
250 	unsigned int last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1);  in qcom_smmu_cfg_probe()
251 	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);  in qcom_smmu_cfg_probe()
265 	arm_smmu_gr0_write(smmu, last_s2cr, reg);  in qcom_smmu_cfg_probe()
266 	reg = arm_smmu_gr0_read(smmu, last_s2cr);  in qcom_smmu_cfg_probe()
269 		qsmmu->bypass_cbndx = smmu->num_context_banks - 1;  in qcom_smmu_cfg_probe()
271 		set_bit(qsmmu->bypass_cbndx, smmu->context_map);  in qcom_smmu_cfg_probe()
273 		arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0);  in qcom_smmu_cfg_probe()
276 		arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg);  in qcom_smmu_cfg_probe()
279 	for (i = 0; i < smmu->num_mapping_groups; i++) {  in qcom_smmu_cfg_probe()
280 		smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i));  in qcom_smmu_cfg_probe()
285 			smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr);  in qcom_smmu_cfg_probe()
286 			smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr);  in qcom_smmu_cfg_probe()
287 			smmu->smrs[i].valid = true;  in qcom_smmu_cfg_probe()
289 			smmu->s2crs[i].type = S2CR_TYPE_BYPASS;  in qcom_smmu_cfg_probe()
290 			smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT;  in qcom_smmu_cfg_probe()
291 			smmu->s2crs[i].cbndx = 0xff;  in qcom_smmu_cfg_probe()
298 static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx)  in qcom_smmu_write_s2cr()  argument
300 	struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx;  in qcom_smmu_write_s2cr()
301 	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);  in qcom_smmu_write_s2cr()
330 	arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg);  in qcom_smmu_write_s2cr()
341 static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)  in qcom_sdm845_smmu500_reset()  argument
353 		dev_warn(smmu->dev, "Failed to turn off SAFE logic\n");  in qcom_sdm845_smmu500_reset()
358 static int qcom_smmu500_reset(struct arm_smmu_device *smmu)  in qcom_smmu500_reset()  argument
360 	const struct device_node *np = smmu->dev->of_node;  in qcom_smmu500_reset()
362 	arm_mmu500_reset(smmu);  in qcom_smmu500_reset()
364 	if (of_device_is_compatible(np, "qcom,sdm845-smmu-500"))  in qcom_smmu500_reset()
365 		return qcom_sdm845_smmu500_reset(smmu);  in qcom_smmu500_reset()
386 static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,  in qcom_smmu_create()  argument
395 	qsmmu = devm_krealloc(smmu->dev, smmu, sizeof(*qsmmu), GFP_KERNEL);  in qcom_smmu_create()
399 	qsmmu->smmu.impl = impl;  in qcom_smmu_create()
401 	return &qsmmu->smmu;  in qcom_smmu_create()
405 	{ .compatible = "qcom,msm8998-smmu-v2" },
406 	{ .compatible = "qcom,sc7180-smmu-500" },
407 	{ .compatible = "qcom,sc7280-smmu-500" },
408 	{ .compatible = "qcom,sc8180x-smmu-500" },
409 	{ .compatible = "qcom,sdm630-smmu-v2" },
410 	{ .compatible = "qcom,sdm845-smmu-500" },
411 	{ .compatible = "qcom,sm6125-smmu-500" },
412 	{ .compatible = "qcom,sm8150-smmu-500" },
413 	{ .compatible = "qcom,sm8250-smmu-500" },
414 	{ .compatible = "qcom,sm8350-smmu-500" },
420 	{ "LENOVO", "CB-01   ", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU" },
421 	{ "QCOM  ", "QCOMEDK2", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU" },
426 struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)  in qcom_smmu_impl_init()  argument
428 	const struct device_node *np = smmu->dev->of_node;  in qcom_smmu_impl_init()
434 			return qcom_smmu_create(smmu, &qcom_smmu_impl);  in qcom_smmu_impl_init()
440 	 * smmu impl and then apss smmu since we can have both implementing  in qcom_smmu_impl_init()
441 	 * arm,mmu-500 in which case we will miss setting adreno smmu specific  in qcom_smmu_impl_init()
444 	if (of_device_is_compatible(np, "qcom,adreno-smmu"))  in qcom_smmu_impl_init()
445 		return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl);  in qcom_smmu_impl_init()
448 		return qcom_smmu_create(smmu, &qcom_smmu_impl);  in qcom_smmu_impl_init()
450 	return smmu;  in qcom_smmu_impl_init()