Lines Matching full:smmu
33 #include "arm-smmu-v3.h"
39 …domain will report an abort back to the device and will not be allowed to pass through the SMMU.");
91 static void parse_driver_options(struct arm_smmu_device *smmu) in parse_driver_options() argument
96 if (of_property_read_bool(smmu->dev->of_node, in parse_driver_options()
98 smmu->options |= arm_smmu_options[i].opt; in parse_driver_options()
99 dev_notice(smmu->dev, "option %s\n", in parse_driver_options()
182 static void queue_poll_init(struct arm_smmu_device *smmu, in queue_poll_init() argument
187 qp->wfe = !!(smmu->features & ARM_SMMU_FEAT_SEV); in queue_poll_init()
338 static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu) in arm_smmu_get_cmdq() argument
340 return &smmu->cmdq; in arm_smmu_get_cmdq()
343 static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, in arm_smmu_cmdq_build_sync_cmd() argument
354 if (smmu->options & ARM_SMMU_OPT_MSIPOLL) { in arm_smmu_cmdq_build_sync_cmd()
362 static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, in __arm_smmu_cmdq_skip_err() argument
380 dev_err(smmu->dev, "CMDQ error (cons 0x%08x): %s\n", cons, in __arm_smmu_cmdq_skip_err()
385 dev_err(smmu->dev, "retrying command fetch\n"); in __arm_smmu_cmdq_skip_err()
407 dev_err(smmu->dev, "skipping command in error state:\n"); in __arm_smmu_cmdq_skip_err()
409 dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd[i]); in __arm_smmu_cmdq_skip_err()
413 dev_err(smmu->dev, "failed to convert to CMD_SYNC\n"); in __arm_smmu_cmdq_skip_err()
420 static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu) in arm_smmu_cmdq_skip_err() argument
422 __arm_smmu_cmdq_skip_err(smmu, &smmu->cmdq.q); in arm_smmu_cmdq_skip_err()
516 * a. If we have MSIs, the SMMU can write back into the CMD_SYNC
586 static int arm_smmu_cmdq_poll_until_not_full(struct arm_smmu_device *smmu, in arm_smmu_cmdq_poll_until_not_full() argument
591 struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu); in arm_smmu_cmdq_poll_until_not_full()
605 queue_poll_init(smmu, &qp); in arm_smmu_cmdq_poll_until_not_full()
618 * Wait until the SMMU signals a CMD_SYNC completion MSI.
621 static int __arm_smmu_cmdq_poll_until_msi(struct arm_smmu_device *smmu, in __arm_smmu_cmdq_poll_until_msi() argument
626 struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu); in __arm_smmu_cmdq_poll_until_msi()
629 queue_poll_init(smmu, &qp); in __arm_smmu_cmdq_poll_until_msi()
642 * Wait until the SMMU cons index passes llq->prod.
645 static int __arm_smmu_cmdq_poll_until_consumed(struct arm_smmu_device *smmu, in __arm_smmu_cmdq_poll_until_consumed() argument
649 struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu); in __arm_smmu_cmdq_poll_until_consumed()
653 queue_poll_init(smmu, &qp); in __arm_smmu_cmdq_poll_until_consumed()
695 static int arm_smmu_cmdq_poll_until_sync(struct arm_smmu_device *smmu, in arm_smmu_cmdq_poll_until_sync() argument
698 if (smmu->options & ARM_SMMU_OPT_MSIPOLL) in arm_smmu_cmdq_poll_until_sync()
699 return __arm_smmu_cmdq_poll_until_msi(smmu, llq); in arm_smmu_cmdq_poll_until_sync()
701 return __arm_smmu_cmdq_poll_until_consumed(smmu, llq); in arm_smmu_cmdq_poll_until_sync()
737 static int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, in arm_smmu_cmdq_issue_cmdlist() argument
744 struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu); in arm_smmu_cmdq_issue_cmdlist()
758 if (arm_smmu_cmdq_poll_until_not_full(smmu, &llq)) in arm_smmu_cmdq_issue_cmdlist()
759 dev_err_ratelimited(smmu->dev, "CMDQ timeout\n"); in arm_smmu_cmdq_issue_cmdlist()
784 arm_smmu_cmdq_build_sync_cmd(cmd_sync, smmu, &cmdq->q, prod); in arm_smmu_cmdq_issue_cmdlist()
800 /* 4. If we are the owner, take control of the SMMU hardware */ in arm_smmu_cmdq_issue_cmdlist()
834 ret = arm_smmu_cmdq_poll_until_sync(smmu, &llq); in arm_smmu_cmdq_issue_cmdlist()
836 dev_err_ratelimited(smmu->dev, in arm_smmu_cmdq_issue_cmdlist()
857 static int __arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu, in __arm_smmu_cmdq_issue_cmd() argument
864 dev_warn(smmu->dev, "ignoring unknown CMDQ opcode 0x%x\n", in __arm_smmu_cmdq_issue_cmd()
869 return arm_smmu_cmdq_issue_cmdlist(smmu, cmd, 1, sync); in __arm_smmu_cmdq_issue_cmd()
872 static int arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu, in arm_smmu_cmdq_issue_cmd() argument
875 return __arm_smmu_cmdq_issue_cmd(smmu, ent, false); in arm_smmu_cmdq_issue_cmd()
878 static int arm_smmu_cmdq_issue_cmd_with_sync(struct arm_smmu_device *smmu, in arm_smmu_cmdq_issue_cmd_with_sync() argument
881 return __arm_smmu_cmdq_issue_cmd(smmu, ent, true); in arm_smmu_cmdq_issue_cmd_with_sync()
884 static void arm_smmu_cmdq_batch_add(struct arm_smmu_device *smmu, in arm_smmu_cmdq_batch_add() argument
889 arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmds, cmds->num, false); in arm_smmu_cmdq_batch_add()
896 static int arm_smmu_cmdq_batch_submit(struct arm_smmu_device *smmu, in arm_smmu_cmdq_batch_submit() argument
899 return arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmds, cmds->num, true); in arm_smmu_cmdq_batch_submit()
929 arm_smmu_cmdq_issue_cmd(master->smmu, &cmd); in arm_smmu_page_response()
941 void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16 asid) in arm_smmu_tlb_inv_asid() argument
944 .opcode = smmu->features & ARM_SMMU_FEAT_E2H ? in arm_smmu_tlb_inv_asid()
949 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_tlb_inv_asid()
959 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_sync_cd() local
974 arm_smmu_cmdq_batch_add(smmu, &cmds, &cmd); in arm_smmu_sync_cd()
979 arm_smmu_cmdq_batch_submit(smmu, &cmds); in arm_smmu_sync_cd()
982 static int arm_smmu_alloc_cd_leaf_table(struct arm_smmu_device *smmu, in arm_smmu_alloc_cd_leaf_table() argument
987 l1_desc->l2ptr = dmam_alloc_coherent(smmu->dev, size, in arm_smmu_alloc_cd_leaf_table()
990 dev_warn(smmu->dev, in arm_smmu_alloc_cd_leaf_table()
1013 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_get_cd_ptr() local
1022 if (arm_smmu_alloc_cd_leaf_table(smmu, l1_desc)) in arm_smmu_get_cd_ptr()
1079 * STE is live, and the SMMU might read dwords of this CD in any in arm_smmu_write_ctx_desc()
1100 * The SMMU accesses 64-bit values atomically. See IHI0070Ca 3.21.3 in arm_smmu_write_ctx_desc()
1103 * The size of single-copy atomic reads made by the SMMU is in arm_smmu_write_ctx_desc()
1118 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_alloc_cd_tables() local
1124 if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB) || in arm_smmu_alloc_cd_tables()
1135 cdcfg->l1_desc = devm_kcalloc(smmu->dev, cdcfg->num_l1_ents, in arm_smmu_alloc_cd_tables()
1144 cdcfg->cdtab = dmam_alloc_coherent(smmu->dev, l1size, &cdcfg->cdtab_dma, in arm_smmu_alloc_cd_tables()
1147 dev_warn(smmu->dev, "failed to allocate context descriptor\n"); in arm_smmu_alloc_cd_tables()
1156 devm_kfree(smmu->dev, cdcfg->l1_desc); in arm_smmu_alloc_cd_tables()
1166 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_free_cd_tables() local
1176 dmam_free_coherent(smmu->dev, size, in arm_smmu_free_cd_tables()
1180 devm_kfree(smmu->dev, cdcfg->l1_desc); in arm_smmu_free_cd_tables()
1188 dmam_free_coherent(smmu->dev, l1size, cdcfg->cdtab, cdcfg->cdtab_dma); in arm_smmu_free_cd_tables()
1222 static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid) in arm_smmu_sync_ste_for_sid() argument
1232 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_sync_ste_for_sid()
1246 * Given that we can't update the STE atomically and the SMMU in arm_smmu_write_strtab_ent()
1256 struct arm_smmu_device *smmu = NULL; in arm_smmu_write_strtab_ent() local
1269 smmu = master->smmu; in arm_smmu_write_strtab_ent()
1317 * The SMMU can perform negative caching, so we must sync in arm_smmu_write_strtab_ent()
1320 if (smmu) in arm_smmu_write_strtab_ent()
1321 arm_smmu_sync_ste_for_sid(smmu, sid); in arm_smmu_write_strtab_ent()
1326 u64 strw = smmu->features & ARM_SMMU_FEAT_E2H ? in arm_smmu_write_strtab_ent()
1337 if (smmu->features & ARM_SMMU_FEAT_STALLS && in arm_smmu_write_strtab_ent()
1367 arm_smmu_sync_ste_for_sid(smmu, sid); in arm_smmu_write_strtab_ent()
1370 arm_smmu_sync_ste_for_sid(smmu, sid); in arm_smmu_write_strtab_ent()
1373 if (!(smmu->options & ARM_SMMU_OPT_SKIP_PREFETCH)) in arm_smmu_write_strtab_ent()
1374 arm_smmu_cmdq_issue_cmd(smmu, &prefetch_cmd); in arm_smmu_write_strtab_ent()
1387 static int arm_smmu_init_l2_strtab(struct arm_smmu_device *smmu, u32 sid) in arm_smmu_init_l2_strtab() argument
1391 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_init_l2_strtab()
1401 desc->l2ptr = dmam_alloc_coherent(smmu->dev, size, &desc->l2ptr_dma, in arm_smmu_init_l2_strtab()
1404 dev_err(smmu->dev, in arm_smmu_init_l2_strtab()
1416 arm_smmu_find_master(struct arm_smmu_device *smmu, u32 sid) in arm_smmu_find_master() argument
1421 lockdep_assert_held(&smmu->streams_mutex); in arm_smmu_find_master()
1423 node = smmu->streams.rb_node; in arm_smmu_find_master()
1438 static int arm_smmu_handle_evt(struct arm_smmu_device *smmu, u64 *evt) in arm_smmu_handle_evt() argument
1509 mutex_lock(&smmu->streams_mutex); in arm_smmu_handle_evt()
1510 master = arm_smmu_find_master(smmu, sid); in arm_smmu_handle_evt()
1528 mutex_unlock(&smmu->streams_mutex); in arm_smmu_handle_evt()
1535 struct arm_smmu_device *smmu = dev; in arm_smmu_evtq_thread() local
1536 struct arm_smmu_queue *q = &smmu->evtq.q; in arm_smmu_evtq_thread()
1546 ret = arm_smmu_handle_evt(smmu, evt); in arm_smmu_evtq_thread()
1550 dev_info(smmu->dev, "event 0x%02x received:\n", id); in arm_smmu_evtq_thread()
1552 dev_info(smmu->dev, "\t0x%016llx\n", in arm_smmu_evtq_thread()
1562 dev_err(smmu->dev, "EVTQ overflow detected -- events lost\n"); in arm_smmu_evtq_thread()
1571 static void arm_smmu_handle_ppr(struct arm_smmu_device *smmu, u64 *evt) in arm_smmu_handle_ppr() argument
1583 dev_info(smmu->dev, "unexpected PRI request received:\n"); in arm_smmu_handle_ppr()
1584 dev_info(smmu->dev, in arm_smmu_handle_ppr()
1605 arm_smmu_cmdq_issue_cmd(smmu, &cmd); in arm_smmu_handle_ppr()
1611 struct arm_smmu_device *smmu = dev; in arm_smmu_priq_thread() local
1612 struct arm_smmu_queue *q = &smmu->priq.q; in arm_smmu_priq_thread()
1618 arm_smmu_handle_ppr(smmu, evt); in arm_smmu_priq_thread()
1621 dev_err(smmu->dev, "PRIQ overflow detected -- requests lost\n"); in arm_smmu_priq_thread()
1631 static int arm_smmu_device_disable(struct arm_smmu_device *smmu);
1636 struct arm_smmu_device *smmu = dev; in arm_smmu_gerror_handler() local
1638 gerror = readl_relaxed(smmu->base + ARM_SMMU_GERROR); in arm_smmu_gerror_handler()
1639 gerrorn = readl_relaxed(smmu->base + ARM_SMMU_GERRORN); in arm_smmu_gerror_handler()
1645 dev_warn(smmu->dev, in arm_smmu_gerror_handler()
1650 dev_err(smmu->dev, "device has entered Service Failure Mode!\n"); in arm_smmu_gerror_handler()
1651 arm_smmu_device_disable(smmu); in arm_smmu_gerror_handler()
1655 dev_warn(smmu->dev, "GERROR MSI write aborted\n"); in arm_smmu_gerror_handler()
1658 dev_warn(smmu->dev, "PRIQ MSI write aborted\n"); in arm_smmu_gerror_handler()
1661 dev_warn(smmu->dev, "EVTQ MSI write aborted\n"); in arm_smmu_gerror_handler()
1664 dev_warn(smmu->dev, "CMDQ MSI write aborted\n"); in arm_smmu_gerror_handler()
1667 dev_err(smmu->dev, "PRIQ write aborted -- events may have been lost\n"); in arm_smmu_gerror_handler()
1670 dev_err(smmu->dev, "EVTQ write aborted -- events may have been lost\n"); in arm_smmu_gerror_handler()
1673 arm_smmu_cmdq_skip_err(smmu); in arm_smmu_gerror_handler()
1675 writel(gerror, smmu->base + ARM_SMMU_GERRORN); in arm_smmu_gerror_handler()
1681 struct arm_smmu_device *smmu = dev; in arm_smmu_combined_irq_thread() local
1684 if (smmu->features & ARM_SMMU_FEAT_PRI) in arm_smmu_combined_irq_thread()
1773 arm_smmu_cmdq_batch_add(master->smmu, &cmds, &cmd); in arm_smmu_atc_inv_master()
1776 return arm_smmu_cmdq_batch_submit(master->smmu, &cmds); in arm_smmu_atc_inv_master()
1788 if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_ATS)) in arm_smmu_atc_inv_domain()
1819 arm_smmu_cmdq_batch_add(smmu_domain->smmu, &cmds, &cmd); in arm_smmu_atc_inv_domain()
1824 return arm_smmu_cmdq_batch_submit(smmu_domain->smmu, &cmds); in arm_smmu_atc_inv_domain()
1831 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_inv_context() local
1837 * to the SMMU. We are relying on the dma_wmb() implicit during cmd in arm_smmu_tlb_inv_context()
1842 arm_smmu_tlb_inv_asid(smmu, smmu_domain->s1_cfg.cd.asid); in arm_smmu_tlb_inv_context()
1846 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_tlb_inv_context()
1856 struct arm_smmu_device *smmu = smmu_domain->smmu; in __arm_smmu_tlb_inv_range() local
1864 if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) { in __arm_smmu_tlb_inv_range()
1880 if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) { in __arm_smmu_tlb_inv_range()
1906 arm_smmu_cmdq_batch_add(smmu, &cmds, cmd); in __arm_smmu_tlb_inv_range()
1909 arm_smmu_cmdq_batch_submit(smmu, &cmds); in __arm_smmu_tlb_inv_range()
1923 cmd.opcode = smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? in arm_smmu_tlb_inv_range_domain()
1944 .opcode = smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? in arm_smmu_tlb_inv_range_asid()
2038 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_domain_free() local
2055 arm_smmu_bitmap_free(smmu->vmid_map, cfg->vmid); in arm_smmu_domain_free()
2067 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_domain_finalise_s1() local
2076 XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL); in arm_smmu_domain_finalise_s1()
2125 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_domain_finalise_s2() local
2129 vmid = arm_smmu_bitmap_alloc(smmu->vmid_map, smmu->vmid_bits); in arm_smmu_domain_finalise_s2()
2158 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_domain_finalise() local
2166 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1)) in arm_smmu_domain_finalise()
2168 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) in arm_smmu_domain_finalise()
2173 ias = (smmu->features & ARM_SMMU_FEAT_VAX) ? 52 : 48; in arm_smmu_domain_finalise()
2175 oas = smmu->ias; in arm_smmu_domain_finalise()
2181 ias = smmu->ias; in arm_smmu_domain_finalise()
2182 oas = smmu->oas; in arm_smmu_domain_finalise()
2191 .pgsize_bitmap = smmu->pgsize_bitmap, in arm_smmu_domain_finalise()
2194 .coherent_walk = smmu->features & ARM_SMMU_FEAT_COHERENCY, in arm_smmu_domain_finalise()
2196 .iommu_dev = smmu->dev, in arm_smmu_domain_finalise()
2217 static __le64 *arm_smmu_get_step_for_sid(struct arm_smmu_device *smmu, u32 sid) in arm_smmu_get_step_for_sid() argument
2220 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_get_step_for_sid()
2222 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { in arm_smmu_get_step_for_sid()
2242 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_install_ste_for_dev() local
2246 __le64 *step = arm_smmu_get_step_for_sid(smmu, sid); in arm_smmu_install_ste_for_dev()
2262 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_ats_supported() local
2265 if (!(smmu->features & ARM_SMMU_FEAT_ATS)) in arm_smmu_ats_supported()
2278 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_enable_ats() local
2286 stu = __ffs(smmu->pgsize_bitmap); in arm_smmu_enable_ats()
2305 * ATC invalidation via the SMMU. in arm_smmu_disable_ats()
2339 master->smmu->ssid_bits); in arm_smmu_enable_pasid()
2383 struct arm_smmu_device *smmu; in arm_smmu_attach_dev() local
2391 smmu = master->smmu; in arm_smmu_attach_dev()
2407 if (!smmu_domain->smmu) { in arm_smmu_attach_dev()
2408 smmu_domain->smmu = smmu; in arm_smmu_attach_dev()
2411 smmu_domain->smmu = NULL; in arm_smmu_attach_dev()
2414 } else if (smmu_domain->smmu != smmu) { in arm_smmu_attach_dev()
2416 "cannot attach to SMMU %s (upstream of %s)\n", in arm_smmu_attach_dev()
2417 dev_name(smmu_domain->smmu->dev), in arm_smmu_attach_dev()
2418 dev_name(smmu->dev)); in arm_smmu_attach_dev()
2483 if (smmu_domain->smmu) in arm_smmu_flush_iotlb_all()
2522 static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, u32 sid) in arm_smmu_sid_in_range() argument
2524 unsigned long limit = smmu->strtab_cfg.num_l1_ents; in arm_smmu_sid_in_range()
2526 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) in arm_smmu_sid_in_range()
2532 static int arm_smmu_insert_master(struct arm_smmu_device *smmu, in arm_smmu_insert_master() argument
2547 mutex_lock(&smmu->streams_mutex); in arm_smmu_insert_master()
2556 * Check the SIDs are in range of the SMMU and our stream table in arm_smmu_insert_master()
2558 if (!arm_smmu_sid_in_range(smmu, sid)) { in arm_smmu_insert_master()
2564 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { in arm_smmu_insert_master()
2565 ret = arm_smmu_init_l2_strtab(smmu, sid); in arm_smmu_insert_master()
2571 new_node = &(smmu->streams.rb_node); in arm_smmu_insert_master()
2592 rb_insert_color(&new_stream->node, &smmu->streams); in arm_smmu_insert_master()
2597 rb_erase(&master->streams[i].node, &smmu->streams); in arm_smmu_insert_master()
2600 mutex_unlock(&smmu->streams_mutex); in arm_smmu_insert_master()
2608 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_remove_master() local
2611 if (!smmu || !master->streams) in arm_smmu_remove_master()
2614 mutex_lock(&smmu->streams_mutex); in arm_smmu_remove_master()
2616 rb_erase(&master->streams[i].node, &smmu->streams); in arm_smmu_remove_master()
2617 mutex_unlock(&smmu->streams_mutex); in arm_smmu_remove_master()
2627 struct arm_smmu_device *smmu; in arm_smmu_probe_device() local
2637 smmu = arm_smmu_get_by_fwnode(fwspec->iommu_fwnode); in arm_smmu_probe_device()
2638 if (!smmu) in arm_smmu_probe_device()
2646 master->smmu = smmu; in arm_smmu_probe_device()
2650 ret = arm_smmu_insert_master(smmu, master); in arm_smmu_probe_device()
2655 master->ssid_bits = min(smmu->ssid_bits, master->ssid_bits); in arm_smmu_probe_device()
2667 if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB)) in arm_smmu_probe_device()
2671 if ((smmu->features & ARM_SMMU_FEAT_STALLS && in arm_smmu_probe_device()
2673 smmu->features & ARM_SMMU_FEAT_STALL_FORCE) in arm_smmu_probe_device()
2676 return &smmu->iommu; in arm_smmu_probe_device()
2694 iopf_queue_remove_device(master->smmu->evtq.iopf, dev); in arm_smmu_release_device()
2725 if (smmu_domain->smmu) in arm_smmu_enable_nesting()
2864 static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu, in arm_smmu_init_one_queue() argument
2875 q->base = dmam_alloc_coherent(smmu->dev, qsz, &q->base_dma, in arm_smmu_init_one_queue()
2884 dev_err(smmu->dev, in arm_smmu_init_one_queue()
2891 dev_info(smmu->dev, "allocated %u entries for %s\n", in arm_smmu_init_one_queue()
2913 static int arm_smmu_cmdq_init(struct arm_smmu_device *smmu) in arm_smmu_cmdq_init() argument
2916 struct arm_smmu_cmdq *cmdq = &smmu->cmdq; in arm_smmu_cmdq_init()
2925 dev_err(smmu->dev, "failed to allocate cmdq bitmap\n"); in arm_smmu_cmdq_init()
2929 devm_add_action(smmu->dev, arm_smmu_cmdq_free_bitmap, bitmap); in arm_smmu_cmdq_init()
2935 static int arm_smmu_init_queues(struct arm_smmu_device *smmu) in arm_smmu_init_queues() argument
2940 ret = arm_smmu_init_one_queue(smmu, &smmu->cmdq.q, smmu->base, in arm_smmu_init_queues()
2946 ret = arm_smmu_cmdq_init(smmu); in arm_smmu_init_queues()
2951 ret = arm_smmu_init_one_queue(smmu, &smmu->evtq.q, smmu->page1, in arm_smmu_init_queues()
2957 if ((smmu->features & ARM_SMMU_FEAT_SVA) && in arm_smmu_init_queues()
2958 (smmu->features & ARM_SMMU_FEAT_STALLS)) { in arm_smmu_init_queues()
2959 smmu->evtq.iopf = iopf_queue_alloc(dev_name(smmu->dev)); in arm_smmu_init_queues()
2960 if (!smmu->evtq.iopf) in arm_smmu_init_queues()
2965 if (!(smmu->features & ARM_SMMU_FEAT_PRI)) in arm_smmu_init_queues()
2968 return arm_smmu_init_one_queue(smmu, &smmu->priq.q, smmu->page1, in arm_smmu_init_queues()
2973 static int arm_smmu_init_l1_strtab(struct arm_smmu_device *smmu) in arm_smmu_init_l1_strtab() argument
2976 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_init_l1_strtab()
2978 void *strtab = smmu->strtab_cfg.strtab; in arm_smmu_init_l1_strtab()
2980 cfg->l1_desc = devm_kzalloc(smmu->dev, size, GFP_KERNEL); in arm_smmu_init_l1_strtab()
2992 static int arm_smmu_init_strtab_2lvl(struct arm_smmu_device *smmu) in arm_smmu_init_strtab_2lvl() argument
2997 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_init_strtab_2lvl()
3001 size = min(size, smmu->sid_bits - STRTAB_SPLIT); in arm_smmu_init_strtab_2lvl()
3005 if (size < smmu->sid_bits) in arm_smmu_init_strtab_2lvl()
3006 dev_warn(smmu->dev, in arm_smmu_init_strtab_2lvl()
3008 size, smmu->sid_bits); in arm_smmu_init_strtab_2lvl()
3011 strtab = dmam_alloc_coherent(smmu->dev, l1size, &cfg->strtab_dma, in arm_smmu_init_strtab_2lvl()
3014 dev_err(smmu->dev, in arm_smmu_init_strtab_2lvl()
3027 return arm_smmu_init_l1_strtab(smmu); in arm_smmu_init_strtab_2lvl()
3030 static int arm_smmu_init_strtab_linear(struct arm_smmu_device *smmu) in arm_smmu_init_strtab_linear() argument
3035 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_init_strtab_linear()
3037 size = (1 << smmu->sid_bits) * (STRTAB_STE_DWORDS << 3); in arm_smmu_init_strtab_linear()
3038 strtab = dmam_alloc_coherent(smmu->dev, size, &cfg->strtab_dma, in arm_smmu_init_strtab_linear()
3041 dev_err(smmu->dev, in arm_smmu_init_strtab_linear()
3047 cfg->num_l1_ents = 1 << smmu->sid_bits; in arm_smmu_init_strtab_linear()
3051 reg |= FIELD_PREP(STRTAB_BASE_CFG_LOG2SIZE, smmu->sid_bits); in arm_smmu_init_strtab_linear()
3058 static int arm_smmu_init_strtab(struct arm_smmu_device *smmu) in arm_smmu_init_strtab() argument
3063 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) in arm_smmu_init_strtab()
3064 ret = arm_smmu_init_strtab_2lvl(smmu); in arm_smmu_init_strtab()
3066 ret = arm_smmu_init_strtab_linear(smmu); in arm_smmu_init_strtab()
3072 reg = smmu->strtab_cfg.strtab_dma & STRTAB_BASE_ADDR_MASK; in arm_smmu_init_strtab()
3074 smmu->strtab_cfg.strtab_base = reg; in arm_smmu_init_strtab()
3077 set_bit(0, smmu->vmid_map); in arm_smmu_init_strtab()
3081 static int arm_smmu_init_structures(struct arm_smmu_device *smmu) in arm_smmu_init_structures() argument
3085 mutex_init(&smmu->streams_mutex); in arm_smmu_init_structures()
3086 smmu->streams = RB_ROOT; in arm_smmu_init_structures()
3088 ret = arm_smmu_init_queues(smmu); in arm_smmu_init_structures()
3092 return arm_smmu_init_strtab(smmu); in arm_smmu_init_structures()
3095 static int arm_smmu_write_reg_sync(struct arm_smmu_device *smmu, u32 val, in arm_smmu_write_reg_sync() argument
3100 writel_relaxed(val, smmu->base + reg_off); in arm_smmu_write_reg_sync()
3101 return readl_relaxed_poll_timeout(smmu->base + ack_off, reg, reg == val, in arm_smmu_write_reg_sync()
3106 static int arm_smmu_update_gbpa(struct arm_smmu_device *smmu, u32 set, u32 clr) in arm_smmu_update_gbpa() argument
3109 u32 reg, __iomem *gbpa = smmu->base + ARM_SMMU_GBPA; in arm_smmu_update_gbpa()
3123 dev_err(smmu->dev, "GBPA not responding to update\n"); in arm_smmu_update_gbpa()
3137 struct arm_smmu_device *smmu = dev_get_drvdata(dev); in arm_smmu_write_msi_msg() local
3143 writeq_relaxed(doorbell, smmu->base + cfg[0]); in arm_smmu_write_msi_msg()
3144 writel_relaxed(msg->data, smmu->base + cfg[1]); in arm_smmu_write_msi_msg()
3145 writel_relaxed(ARM_SMMU_MEMATTR_DEVICE_nGnRE, smmu->base + cfg[2]); in arm_smmu_write_msi_msg()
3148 static void arm_smmu_setup_msis(struct arm_smmu_device *smmu) in arm_smmu_setup_msis() argument
3152 struct device *dev = smmu->dev; in arm_smmu_setup_msis()
3155 writeq_relaxed(0, smmu->base + ARM_SMMU_GERROR_IRQ_CFG0); in arm_smmu_setup_msis()
3156 writeq_relaxed(0, smmu->base + ARM_SMMU_EVTQ_IRQ_CFG0); in arm_smmu_setup_msis()
3158 if (smmu->features & ARM_SMMU_FEAT_PRI) in arm_smmu_setup_msis()
3159 writeq_relaxed(0, smmu->base + ARM_SMMU_PRIQ_IRQ_CFG0); in arm_smmu_setup_msis()
3163 if (!(smmu->features & ARM_SMMU_FEAT_MSI)) in arm_smmu_setup_msis()
3167 dev_info(smmu->dev, "msi_domain absent - falling back to wired irqs\n"); in arm_smmu_setup_msis()
3181 smmu->evtq.q.irq = desc->irq; in arm_smmu_setup_msis()
3184 smmu->gerr_irq = desc->irq; in arm_smmu_setup_msis()
3187 smmu->priq.q.irq = desc->irq; in arm_smmu_setup_msis()
3198 static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu) in arm_smmu_setup_unique_irqs() argument
3202 arm_smmu_setup_msis(smmu); in arm_smmu_setup_unique_irqs()
3205 irq = smmu->evtq.q.irq; in arm_smmu_setup_unique_irqs()
3207 ret = devm_request_threaded_irq(smmu->dev, irq, NULL, in arm_smmu_setup_unique_irqs()
3210 "arm-smmu-v3-evtq", smmu); in arm_smmu_setup_unique_irqs()
3212 dev_warn(smmu->dev, "failed to enable evtq irq\n"); in arm_smmu_setup_unique_irqs()
3214 dev_warn(smmu->dev, "no evtq irq - events will not be reported!\n"); in arm_smmu_setup_unique_irqs()
3217 irq = smmu->gerr_irq; in arm_smmu_setup_unique_irqs()
3219 ret = devm_request_irq(smmu->dev, irq, arm_smmu_gerror_handler, in arm_smmu_setup_unique_irqs()
3220 0, "arm-smmu-v3-gerror", smmu); in arm_smmu_setup_unique_irqs()
3222 dev_warn(smmu->dev, "failed to enable gerror irq\n"); in arm_smmu_setup_unique_irqs()
3224 dev_warn(smmu->dev, "no gerr irq - errors will not be reported!\n"); in arm_smmu_setup_unique_irqs()
3227 if (smmu->features & ARM_SMMU_FEAT_PRI) { in arm_smmu_setup_unique_irqs()
3228 irq = smmu->priq.q.irq; in arm_smmu_setup_unique_irqs()
3230 ret = devm_request_threaded_irq(smmu->dev, irq, NULL, in arm_smmu_setup_unique_irqs()
3233 "arm-smmu-v3-priq", in arm_smmu_setup_unique_irqs()
3234 smmu); in arm_smmu_setup_unique_irqs()
3236 dev_warn(smmu->dev, in arm_smmu_setup_unique_irqs()
3239 dev_warn(smmu->dev, "no priq irq - PRI will be broken\n"); in arm_smmu_setup_unique_irqs()
3244 static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu) in arm_smmu_setup_irqs() argument
3250 ret = arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_IRQ_CTRL, in arm_smmu_setup_irqs()
3253 dev_err(smmu->dev, "failed to disable irqs\n"); in arm_smmu_setup_irqs()
3257 irq = smmu->combined_irq; in arm_smmu_setup_irqs()
3263 ret = devm_request_threaded_irq(smmu->dev, irq, in arm_smmu_setup_irqs()
3267 "arm-smmu-v3-combined-irq", smmu); in arm_smmu_setup_irqs()
3269 dev_warn(smmu->dev, "failed to enable combined irq\n"); in arm_smmu_setup_irqs()
3271 arm_smmu_setup_unique_irqs(smmu); in arm_smmu_setup_irqs()
3273 if (smmu->features & ARM_SMMU_FEAT_PRI) in arm_smmu_setup_irqs()
3276 /* Enable interrupt generation on the SMMU */ in arm_smmu_setup_irqs()
3277 ret = arm_smmu_write_reg_sync(smmu, irqen_flags, in arm_smmu_setup_irqs()
3280 dev_warn(smmu->dev, "failed to enable irqs\n"); in arm_smmu_setup_irqs()
3285 static int arm_smmu_device_disable(struct arm_smmu_device *smmu) in arm_smmu_device_disable() argument
3289 ret = arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_CR0, ARM_SMMU_CR0ACK); in arm_smmu_device_disable()
3291 dev_err(smmu->dev, "failed to clear cr0\n"); in arm_smmu_device_disable()
3296 static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool bypass) in arm_smmu_device_reset() argument
3302 /* Clear CR0 and sync (disables SMMU and queue processing) */ in arm_smmu_device_reset()
3303 reg = readl_relaxed(smmu->base + ARM_SMMU_CR0); in arm_smmu_device_reset()
3305 dev_warn(smmu->dev, "SMMU currently enabled! Resetting...\n"); in arm_smmu_device_reset()
3307 arm_smmu_update_gbpa(smmu, GBPA_ABORT, 0); in arm_smmu_device_reset()
3310 ret = arm_smmu_device_disable(smmu); in arm_smmu_device_reset()
3321 writel_relaxed(reg, smmu->base + ARM_SMMU_CR1); in arm_smmu_device_reset()
3326 if (smmu->features & ARM_SMMU_FEAT_E2H) in arm_smmu_device_reset()
3329 writel_relaxed(reg, smmu->base + ARM_SMMU_CR2); in arm_smmu_device_reset()
3332 writeq_relaxed(smmu->strtab_cfg.strtab_base, in arm_smmu_device_reset()
3333 smmu->base + ARM_SMMU_STRTAB_BASE); in arm_smmu_device_reset()
3334 writel_relaxed(smmu->strtab_cfg.strtab_base_cfg, in arm_smmu_device_reset()
3335 smmu->base + ARM_SMMU_STRTAB_BASE_CFG); in arm_smmu_device_reset()
3338 writeq_relaxed(smmu->cmdq.q.q_base, smmu->base + ARM_SMMU_CMDQ_BASE); in arm_smmu_device_reset()
3339 writel_relaxed(smmu->cmdq.q.llq.prod, smmu->base + ARM_SMMU_CMDQ_PROD); in arm_smmu_device_reset()
3340 writel_relaxed(smmu->cmdq.q.llq.cons, smmu->base + ARM_SMMU_CMDQ_CONS); in arm_smmu_device_reset()
3343 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, in arm_smmu_device_reset()
3346 dev_err(smmu->dev, "failed to enable command queue\n"); in arm_smmu_device_reset()
3352 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_device_reset()
3355 if (smmu->features & ARM_SMMU_FEAT_HYP) { in arm_smmu_device_reset()
3357 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_device_reset()
3361 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_device_reset()
3364 writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE); in arm_smmu_device_reset()
3365 writel_relaxed(smmu->evtq.q.llq.prod, smmu->page1 + ARM_SMMU_EVTQ_PROD); in arm_smmu_device_reset()
3366 writel_relaxed(smmu->evtq.q.llq.cons, smmu->page1 + ARM_SMMU_EVTQ_CONS); in arm_smmu_device_reset()
3369 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, in arm_smmu_device_reset()
3372 dev_err(smmu->dev, "failed to enable event queue\n"); in arm_smmu_device_reset()
3377 if (smmu->features & ARM_SMMU_FEAT_PRI) { in arm_smmu_device_reset()
3378 writeq_relaxed(smmu->priq.q.q_base, in arm_smmu_device_reset()
3379 smmu->base + ARM_SMMU_PRIQ_BASE); in arm_smmu_device_reset()
3380 writel_relaxed(smmu->priq.q.llq.prod, in arm_smmu_device_reset()
3381 smmu->page1 + ARM_SMMU_PRIQ_PROD); in arm_smmu_device_reset()
3382 writel_relaxed(smmu->priq.q.llq.cons, in arm_smmu_device_reset()
3383 smmu->page1 + ARM_SMMU_PRIQ_CONS); in arm_smmu_device_reset()
3386 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, in arm_smmu_device_reset()
3389 dev_err(smmu->dev, "failed to enable PRI queue\n"); in arm_smmu_device_reset()
3394 if (smmu->features & ARM_SMMU_FEAT_ATS) { in arm_smmu_device_reset()
3396 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, in arm_smmu_device_reset()
3399 dev_err(smmu->dev, "failed to enable ATS check\n"); in arm_smmu_device_reset()
3404 ret = arm_smmu_setup_irqs(smmu); in arm_smmu_device_reset()
3406 dev_err(smmu->dev, "failed to setup irqs\n"); in arm_smmu_device_reset()
3413 /* Enable the SMMU interface, or ensure bypass */ in arm_smmu_device_reset()
3417 ret = arm_smmu_update_gbpa(smmu, 0, GBPA_ABORT); in arm_smmu_device_reset()
3421 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, in arm_smmu_device_reset()
3424 dev_err(smmu->dev, "failed to enable SMMU interface\n"); in arm_smmu_device_reset()
3431 static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) in arm_smmu_device_hw_probe() argument
3434 bool coherent = smmu->features & ARM_SMMU_FEAT_COHERENCY; in arm_smmu_device_hw_probe()
3437 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR0); in arm_smmu_device_hw_probe()
3441 smmu->features |= ARM_SMMU_FEAT_2_LVL_STRTAB; in arm_smmu_device_hw_probe()
3444 smmu->features |= ARM_SMMU_FEAT_2_LVL_CDTAB; in arm_smmu_device_hw_probe()
3453 smmu->features |= ARM_SMMU_FEAT_TT_LE | ARM_SMMU_FEAT_TT_BE; in arm_smmu_device_hw_probe()
3457 smmu->features |= ARM_SMMU_FEAT_TT_BE; in arm_smmu_device_hw_probe()
3461 smmu->features |= ARM_SMMU_FEAT_TT_LE; in arm_smmu_device_hw_probe()
3465 dev_err(smmu->dev, "unknown/unsupported TT endianness!\n"); in arm_smmu_device_hw_probe()
3471 smmu->features |= ARM_SMMU_FEAT_PRI; in arm_smmu_device_hw_probe()
3474 smmu->features |= ARM_SMMU_FEAT_ATS; in arm_smmu_device_hw_probe()
3477 smmu->features |= ARM_SMMU_FEAT_SEV; in arm_smmu_device_hw_probe()
3480 smmu->features |= ARM_SMMU_FEAT_MSI; in arm_smmu_device_hw_probe()
3482 smmu->options |= ARM_SMMU_OPT_MSIPOLL; in arm_smmu_device_hw_probe()
3486 smmu->features |= ARM_SMMU_FEAT_HYP; in arm_smmu_device_hw_probe()
3488 smmu->features |= ARM_SMMU_FEAT_E2H; in arm_smmu_device_hw_probe()
3496 dev_warn(smmu->dev, "IDR0.COHACC overridden by FW configuration (%s)\n", in arm_smmu_device_hw_probe()
3501 smmu->features |= ARM_SMMU_FEAT_STALL_FORCE; in arm_smmu_device_hw_probe()
3504 smmu->features |= ARM_SMMU_FEAT_STALLS; in arm_smmu_device_hw_probe()
3508 smmu->features |= ARM_SMMU_FEAT_TRANS_S1; in arm_smmu_device_hw_probe()
3511 smmu->features |= ARM_SMMU_FEAT_TRANS_S2; in arm_smmu_device_hw_probe()
3514 dev_err(smmu->dev, "no translation support!\n"); in arm_smmu_device_hw_probe()
3521 smmu->ias = 40; in arm_smmu_device_hw_probe()
3526 dev_err(smmu->dev, "AArch64 table format not supported!\n"); in arm_smmu_device_hw_probe()
3531 smmu->asid_bits = reg & IDR0_ASID16 ? 16 : 8; in arm_smmu_device_hw_probe()
3532 smmu->vmid_bits = reg & IDR0_VMID16 ? 16 : 8; in arm_smmu_device_hw_probe()
3535 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR1); in arm_smmu_device_hw_probe()
3537 dev_err(smmu->dev, "embedded implementation not supported\n"); in arm_smmu_device_hw_probe()
3542 smmu->cmdq.q.llq.max_n_shift = min_t(u32, CMDQ_MAX_SZ_SHIFT, in arm_smmu_device_hw_probe()
3544 if (smmu->cmdq.q.llq.max_n_shift <= ilog2(CMDQ_BATCH_ENTRIES)) { in arm_smmu_device_hw_probe()
3551 dev_err(smmu->dev, "command queue size <= %d entries not supported\n", in arm_smmu_device_hw_probe()
3556 smmu->evtq.q.llq.max_n_shift = min_t(u32, EVTQ_MAX_SZ_SHIFT, in arm_smmu_device_hw_probe()
3558 smmu->priq.q.llq.max_n_shift = min_t(u32, PRIQ_MAX_SZ_SHIFT, in arm_smmu_device_hw_probe()
3562 smmu->ssid_bits = FIELD_GET(IDR1_SSIDSIZE, reg); in arm_smmu_device_hw_probe()
3563 smmu->sid_bits = FIELD_GET(IDR1_SIDSIZE, reg); in arm_smmu_device_hw_probe()
3566 * If the SMMU supports fewer bits than would fill a single L2 stream in arm_smmu_device_hw_probe()
3569 if (smmu->sid_bits <= STRTAB_SPLIT) in arm_smmu_device_hw_probe()
3570 smmu->features &= ~ARM_SMMU_FEAT_2_LVL_STRTAB; in arm_smmu_device_hw_probe()
3573 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR3); in arm_smmu_device_hw_probe()
3575 smmu->features |= ARM_SMMU_FEAT_RANGE_INV; in arm_smmu_device_hw_probe()
3578 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR5); in arm_smmu_device_hw_probe()
3581 smmu->evtq.max_stalls = FIELD_GET(IDR5_STALL_MAX, reg); in arm_smmu_device_hw_probe()
3585 smmu->pgsize_bitmap |= SZ_64K | SZ_512M; in arm_smmu_device_hw_probe()
3587 smmu->pgsize_bitmap |= SZ_16K | SZ_32M; in arm_smmu_device_hw_probe()
3589 smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G; in arm_smmu_device_hw_probe()
3593 smmu->features |= ARM_SMMU_FEAT_VAX; in arm_smmu_device_hw_probe()
3598 smmu->oas = 32; in arm_smmu_device_hw_probe()
3601 smmu->oas = 36; in arm_smmu_device_hw_probe()
3604 smmu->oas = 40; in arm_smmu_device_hw_probe()
3607 smmu->oas = 42; in arm_smmu_device_hw_probe()
3610 smmu->oas = 44; in arm_smmu_device_hw_probe()
3613 smmu->oas = 52; in arm_smmu_device_hw_probe()
3614 smmu->pgsize_bitmap |= 1ULL << 42; /* 4TB */ in arm_smmu_device_hw_probe()
3617 dev_info(smmu->dev, in arm_smmu_device_hw_probe()
3621 smmu->oas = 48; in arm_smmu_device_hw_probe()
3625 arm_smmu_ops.pgsize_bitmap = smmu->pgsize_bitmap; in arm_smmu_device_hw_probe()
3627 arm_smmu_ops.pgsize_bitmap |= smmu->pgsize_bitmap; in arm_smmu_device_hw_probe()
3630 if (dma_set_mask_and_coherent(smmu->dev, DMA_BIT_MASK(smmu->oas))) in arm_smmu_device_hw_probe()
3631 dev_warn(smmu->dev, in arm_smmu_device_hw_probe()
3634 smmu->ias = max(smmu->ias, smmu->oas); in arm_smmu_device_hw_probe()
3636 if (arm_smmu_sva_supported(smmu)) in arm_smmu_device_hw_probe()
3637 smmu->features |= ARM_SMMU_FEAT_SVA; in arm_smmu_device_hw_probe()
3639 dev_info(smmu->dev, "ias %lu-bit, oas %lu-bit (features 0x%08x)\n", in arm_smmu_device_hw_probe()
3640 smmu->ias, smmu->oas, smmu->features); in arm_smmu_device_hw_probe()
3645 static void acpi_smmu_get_options(u32 model, struct arm_smmu_device *smmu) in acpi_smmu_get_options() argument
3649 smmu->options |= ARM_SMMU_OPT_PAGE0_REGS_ONLY; in acpi_smmu_get_options()
3652 smmu->options |= ARM_SMMU_OPT_SKIP_PREFETCH; in acpi_smmu_get_options()
3656 dev_notice(smmu->dev, "option mask 0x%x\n", smmu->options); in acpi_smmu_get_options()
3660 struct arm_smmu_device *smmu) in arm_smmu_device_acpi_probe() argument
3663 struct device *dev = smmu->dev; in arm_smmu_device_acpi_probe()
3671 acpi_smmu_get_options(iort_smmu->model, smmu); in arm_smmu_device_acpi_probe()
3674 smmu->features |= ARM_SMMU_FEAT_COHERENCY; in arm_smmu_device_acpi_probe()
3680 struct arm_smmu_device *smmu) in arm_smmu_device_acpi_probe() argument
3687 struct arm_smmu_device *smmu) in arm_smmu_device_dt_probe() argument
3700 parse_driver_options(smmu); in arm_smmu_device_dt_probe()
3703 smmu->features |= ARM_SMMU_FEAT_COHERENCY; in arm_smmu_device_dt_probe()
3708 static unsigned long arm_smmu_resource_size(struct arm_smmu_device *smmu) in arm_smmu_resource_size() argument
3710 if (smmu->options & ARM_SMMU_OPT_PAGE0_REGS_ONLY) in arm_smmu_resource_size()
3766 struct arm_smmu_device *smmu; in arm_smmu_device_probe() local
3770 smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); in arm_smmu_device_probe()
3771 if (!smmu) in arm_smmu_device_probe()
3773 smmu->dev = dev; in arm_smmu_device_probe()
3776 ret = arm_smmu_device_dt_probe(pdev, smmu); in arm_smmu_device_probe()
3778 ret = arm_smmu_device_acpi_probe(pdev, smmu); in arm_smmu_device_probe()
3788 if (resource_size(res) < arm_smmu_resource_size(smmu)) { in arm_smmu_device_probe()
3798 smmu->base = arm_smmu_ioremap(dev, ioaddr, ARM_SMMU_REG_SZ); in arm_smmu_device_probe()
3799 if (IS_ERR(smmu->base)) in arm_smmu_device_probe()
3800 return PTR_ERR(smmu->base); in arm_smmu_device_probe()
3802 if (arm_smmu_resource_size(smmu) > SZ_64K) { in arm_smmu_device_probe()
3803 smmu->page1 = arm_smmu_ioremap(dev, ioaddr + SZ_64K, in arm_smmu_device_probe()
3805 if (IS_ERR(smmu->page1)) in arm_smmu_device_probe()
3806 return PTR_ERR(smmu->page1); in arm_smmu_device_probe()
3808 smmu->page1 = smmu->base; in arm_smmu_device_probe()
3815 smmu->combined_irq = irq; in arm_smmu_device_probe()
3819 smmu->evtq.q.irq = irq; in arm_smmu_device_probe()
3823 smmu->priq.q.irq = irq; in arm_smmu_device_probe()
3827 smmu->gerr_irq = irq; in arm_smmu_device_probe()
3830 ret = arm_smmu_device_hw_probe(smmu); in arm_smmu_device_probe()
3835 ret = arm_smmu_init_structures(smmu); in arm_smmu_device_probe()
3840 platform_set_drvdata(pdev, smmu); in arm_smmu_device_probe()
3843 ret = arm_smmu_device_reset(smmu, bypass); in arm_smmu_device_probe()
3848 ret = iommu_device_sysfs_add(&smmu->iommu, dev, NULL, in arm_smmu_device_probe()
3853 ret = iommu_device_register(&smmu->iommu, &arm_smmu_ops, dev); in arm_smmu_device_probe()
3866 iommu_device_unregister(&smmu->iommu); in arm_smmu_device_probe()
3868 iommu_device_sysfs_remove(&smmu->iommu); in arm_smmu_device_probe()
3874 struct arm_smmu_device *smmu = platform_get_drvdata(pdev); in arm_smmu_device_remove() local
3877 iommu_device_unregister(&smmu->iommu); in arm_smmu_device_remove()
3878 iommu_device_sysfs_remove(&smmu->iommu); in arm_smmu_device_remove()
3879 arm_smmu_device_disable(smmu); in arm_smmu_device_remove()
3880 iopf_queue_free(smmu->evtq.iopf); in arm_smmu_device_remove()
3891 { .compatible = "arm,smmu-v3", },
3904 .name = "arm-smmu-v3",
3917 MODULE_ALIAS("platform:arm-smmu-v3");