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/Linux-v5.4/Documentation/devicetree/bindings/arm/
Dsecure.txt1 * ARM Secure world bindings
4 "Normal" and "Secure". Most devicetree consumers (including the Linux
6 world or the Secure world. However some devicetree consumers are
8 visible only in the Secure address space, only in the Normal address
10 virtual machine which boots Secure firmware and wants to tell the
13 The general principle of the naming scheme for Secure world bindings
14 is that any property that needs a different value in the Secure world
15 can be supported by prefixing the property name with "secure-". So for
16 instance "secure-foo" would override "foo". For property names with
17 a vendor prefix, the Secure variant of "vendor,foo" would be
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Dpmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - arm,armv8-pmuv3
24 - arm,cortex-a73-pmu
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Djuno,scpi.txt5 ------------------------------------
8 - compatible : should be "arm,juno-sram-ns" for Non-secure SRAM
10 Each sub-node represents the reserved area for SCPI.
12 Required sub-node properties:
13 - reg : The base offset and size of the reserved area with the SRAM
14 - compatible : should be "arm,juno-scp-shmem" for Non-secure SRAM based
18 --------------------------------------------------------------
20 - compatible : should be "arm,scpi-sensors".
21 - #thermal-sensor-cells: should be set to 1.
/Linux-v5.4/Documentation/devicetree/bindings/iommu/
Dqcom,iommu.txt3 Qualcomm "B" family devices which are not compatible with arm-smmu have
6 to non-secure vs secure interrupt line.
10 - compatible : Should be one of:
12 "qcom,msm8916-iommu"
14 Followed by "qcom,msm-iommu-v1".
16 - clock-names : Should be a pair of "iface" (required for IOMMUs
20 - clocks : Phandles for respective clocks described by
21 clock-names.
23 - #address-cells : must be 1.
25 - #size-cells : must be 1.
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Dmsm,iommu-v0.txt5 of the CPU, each connected to the IOMMU through a port called micro-TLB.
9 - compatible: Must contain "qcom,apq8064-iommu".
10 - reg: Base address and size of the IOMMU registers.
11 - interrupts: Specifiers for the MMU fault interrupts. For instances that
12 support secure mode two interrupts must be specified, for non-secure and
13 secure mode, in that order. For instances that don't support secure mode a
15 - #iommu-cells: The number of cells needed to specify the stream id. This
17 - qcom,ncb: The total number of context banks in the IOMMU.
18 - clocks : List of clocks to be used during SMMU register access. See
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
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Drenesas,ipmmu-vmsa.txt1 * Renesas VMSA-Compatible IOMMU
5 connected to the IPMMU through a port called micro-TLB.
10 - compatible: Must contain SoC-specific and generic entry below in case
11 the device is compatible with the R-Car Gen2 VMSA-compatible IPMMU.
13 - "renesas,ipmmu-r8a73a4" for the R8A73A4 (R-Mobile APE6) IPMMU.
14 - "renesas,ipmmu-r8a7743" for the R8A7743 (RZ/G1M) IPMMU.
15 - "renesas,ipmmu-r8a7744" for the R8A7744 (RZ/G1N) IPMMU.
16 - "renesas,ipmmu-r8a7745" for the R8A7745 (RZ/G1E) IPMMU.
17 - "renesas,ipmmu-r8a774a1" for the R8A774A1 (RZ/G2M) IPMMU.
18 - "renesas,ipmmu-r8a774c0" for the R8A774C0 (RZ/G2E) IPMMU.
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/Linux-v5.4/arch/arm/common/
Dsecure_cntvoff.S1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Initialization of CNTVOFF register from secure mode
13 .arch armv7-a
15 * CNTVOFF has to be initialized either from non-secure Hypervisor
16 * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
17 * then it should be handled by the secure code. The CPU must implement
21 mrc p15, 0, r1, c1, c1, 0 /* Get Secure Config */
23 mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */
28 mcr p15, 0, r1, c1, c1, 0 /* Set Secure bit */
/Linux-v5.4/arch/arm/mach-omap2/
Domap-secure.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP Secure API infrastructure.
19 #include "omap-secure.h"
24 * omap_sec_dispatcher: Routine to dispatch low power secure
29 * @arg1, arg2, arg3 args4: Parameters passed to secure API
31 * Return the non-zero error value on failure.
46 * Secure API needs physical address in omap_secure_dispatcher()
56 /* Allocate the memory to save secure ram */
94 * rx51_secure_dispatcher: Routine to dispatch secure PPA API calls
99 * @arg1, arg2, arg3 args4: Parameters passed to secure API
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Domap-headsmp.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2009-2014 Texas Instruments, Inc.
58 .arch armv7-a
110 * CortexA9 r1pX and r2pX. The Control Register secure
112 * bit 0 == Secure Enable
113 * bit 1 == Non-Secure Enable
114 * The Non-Secure banked register has not changed
116 * GIC restoration will cause a problem to CPU0 Non-Secure SW.
120 * 2) CPU1 must re-enable the GIC distributor on
Domap-smp.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <linux/irqchip/arm-gic.h>
25 #include "omap-secure.h"
26 #include "omap-wakeupgen.h"
87 * BIT(27) - Disables streaming. All write-allocate lines allocate in in omap5_erratum_workaround_801819()
89 * BIT(25) - Disables streaming. All write-allocate lines allocate in in omap5_erratum_workaround_801819()
116 * by ROM code in "secure world" using the smc call and there is no
150 * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA in omap4_secondary_init()
151 * init and for CPU1, a secure PPA API provided. CPU0 must be ON in omap4_secondary_init()
153 * OMAP443X GP devices- SMP bit isn't accessible. in omap4_secondary_init()
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/Linux-v5.4/drivers/tee/optee/
Doptee_smc.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
3 * Copyright (c) 2015-2019, Linaro Limited
8 #include <linux/arm-smccc.h>
28 * Normal cached memory (write-back), shareable for SMP systems and not
36 * 32-bit registers.
44 * 65cb6b93-af0c-4617-8ed6-644a8d1140f8
75 * Used by non-secure world to figure out which Trusted OS is installed.
78 * Returns UUID in a0-4 in the same way as OPTEE_SMC_CALLS_UID
88 * Used by non-secure world to figure out which version of the Trusted OS
92 * Returns revision in a0-1 in the same way as OPTEE_SMC_CALLS_REVISION
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Doptee_msg.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
3 * Copyright (c) 2015-2019, Linaro Limited
12 * This file defines the OP-TEE message protocol used to communicate
13 * with an instance of OP-TEE running in secure world.
18 * 3. Requests from secure world, Remote Procedure Call (RPC), handled by
19 * tee-supplicant.
23 * Part 1 - formatting of messages
40 * Meta parameter to be absorbed by the Secure OS and not passed
48 * Pointer to a list of pages used to register user-defined SHM buffer.
51 * list of page addresses. OP-TEE core can reconstruct contiguous buffer from
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/Linux-v5.4/Documentation/devicetree/bindings/sram/
Dsamsung-sram.txt2 ------------------------------------
4 Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup
8 Therefore reserved section sub-nodes have to be added to the mmio-sram
9 declaration. These nodes are of two types depending upon secure or
10 non-secure execution environment.
12 Required sub-node properties:
13 - compatible : depending upon boot mode, should be
14 "samsung,exynos4210-sysram" : for Secure SYSRAM
15 "samsung,exynos4210-sysram-ns" : for Non-secure SYSRAM
17 The rest of the properties should follow the generic mmio-sram discription
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/Linux-v5.4/drivers/vfio/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
23 tristate "VFIO Non-Privileged userspace driver framework"
27 VFIO provides a framework for secure userspace device drivers.
28 See Documentation/driver-api/vfio.rst for more details.
33 bool "VFIO No-IOMMU support"
38 considered secure. VFIO No-IOMMU mode enables IOMMU groups for
39 devices without IOMMU backing for the purpose of re-using the VFIO
40 infrastructure in a non-secure mode. Use of this mode will result
/Linux-v5.4/Documentation/devicetree/bindings/misc/
Dbrcm,kona-smc.txt1 Broadcom Secure Monitor Bounce buffer
2 -----------------------------------------------------
4 used for non-secure to secure communications.
7 - compatible : "brcm,kona-smc"
8 - DEPRECATED: compatible : "bcm,kona-smc"
9 - reg : Location and size of bounce buffer
13 compatible = "brcm,bcm11351-smc", "brcm,kona-smc";
/Linux-v5.4/Documentation/arm64/
Dbooting.rst13 (EL0 - EL3), with EL0 and EL1 having a secure and a non-secure
14 counterpart. EL2 is the hypervisor level and exists only in non-secure
15 mode. EL3 is the highest priority level and exists only in secure mode.
19 is passed to the Linux kernel. This may include secure monitor and
33 ---------------------------
46 -------------------------
50 The device tree blob (dtb) must be placed on an 8-byte boundary and must
59 ------------------------------
71 ------------------------
75 The decompressed kernel image contains a 64-byte header as follows::
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/Linux-v5.4/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/
Dacr_r361.h29 * struct acr_r361_flcn_bl_desc - DMEM bootloader descriptor
30 * @signature: 16B signature for secure code. 0s if no secure code
32 * @code_dma_base: 256B-aligned Physical FB Address where code is located
34 * @non_sec_code_off: offset from code_dma_base where the non-secure code is
37 * @sec_code_off: offset from code_dma_base where the secure code is
39 * @sec_code_size: offset from code_dma_base where the secure code is
Dbase.c24 * Secure boot is the process by which NVIDIA-signed firmware is loaded into
31 * - Non-secure (NS). In this mode, functionality is similar to Falcon
32 * architectures before security modes were introduced (pre-Maxwell), but
38 * - Heavy Secure (HS). In this mode, the microprocessor is a black box - it's
42 * (The loading process involves tagging the IMEM block as secure, writing the
46 * - Light Secure (LS). In this mode, the microprocessor has more privileges
52 * Secure boot consists in temporarily switching a HS-capable falcon (typically
54 * load them, and switch managed falcons into LS mode. Once secure boot
57 * Secure boot requires a write-protected memory region (WPR) which can only be
58 * written by the secure falcon. On dGPU, the driver sets up the WPR region in
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/Linux-v5.4/Documentation/arm/samsung/
Dbootloader-interface.rst14 In the document "boot loader" means any of following: U-boot, proprietary
19 1. Non-Secure mode
37 2. Secure mode
65 3. Other (regardless of secure/non-secure mode)
72 0x0908 Non-zero Secondary CPU boot up indicator
79 AFTR - ARM Off Top Running, a low power mode, Cortex cores and many other
81 MCPM - Multi-Cluster Power Management
/Linux-v5.4/drivers/rtc/
Drtc-mxc_v2.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2004-2011 Freescale Semiconductor, Inc.
21 #define SRTC_LPCR_NSA BIT(11) /* lp non secure access */
22 #define SRTC_LPCR_NVE BIT(14) /* lp non valid state exit bit */
26 #define SRTC_LPSR_NVES BIT(14) /* lp non-valid state exit status */
29 #define SRTC_LPSCMR 0x00 /* LP Secure Counter MSB Reg */
30 #define SRTC_LPSCLR 0x04 /* LP Secure Counter LSB Reg */
31 #define SRTC_LPSAR 0x08 /* LP Secure Alarm Reg */
51 * The caller should hold the pdata->lock
63 if (!--timeout) { in mxc_rtc_sync_lp_locked()
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/Linux-v5.4/crypto/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
142 bool "Disable run-time self tests"
145 Disable run-time self tests that normally take place at
149 bool "Enable extra run-time crypto self tests"
152 Enable extra run-time self tests of registered crypto algorithms,
225 comment "Public-key cryptography"
237 tristate "Diffie-Hellman algorithm"
241 Generic implementation of the Diffie-Hellman algorithm.
255 tristate "EC-RDSA (GOST 34.10) algorithm"
262 Elliptic Curve Russian Digital Signature Algorithm (GOST R 34.10-2012,
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/Linux-v5.4/arch/arm/mach-sti/
Dboard-dt.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <asm/hardware/cache-l2x0.h>
26 * We can't write to secure registers as we are in non-secure in sti_l2_write_sec()
/Linux-v5.4/include/linux/firmware/intel/
Dstratix10-smc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2017-2018, Intel Corporation
9 #include <linux/arm-smccc.h>
13 * This file defines the Secure Monitor Call (SMC) message protocol used for
14 * service layer driver in normal world (EL1) to communicate with secure
15 * monitor software in Secure Monitor Exception Level 3 (EL3).
17 * This file is shared with secure firmware (FW) which is out of kernel tree.
19 * An ARM SMC instruction takes a function identifier and up to 6 64-bit
20 * register values as arguments, and can return up to 4 64-bit register
21 * value. The operation of the secure monitor is determined by the parameter
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/Linux-v5.4/Documentation/devicetree/bindings/arm/samsung/
Dsamsung-boards.txt4 - compatible = should be one or more of the following.
5 - "samsung,aries" - for S5PV210-based Samsung Aries board.
6 - "samsung,fascinate4g" - for S5PV210-based Samsung Galaxy S Fascinate 4G (SGH-T959P) board.
7 - "samsung,galaxys" - for S5PV210-based Samsung Galaxy S (i9000) board.
8 - "samsung,artik5" - for Exynos3250-based Samsung ARTIK5 module.
9 - "samsung,artik5-eval" - for Exynos3250-based Samsung ARTIK5 eval board.
10 - "samsung,monk" - for Exynos3250-based Samsung Simband board.
11 - "samsung,rinato" - for Exynos3250-based Samsung Gear2 board.
12 - "samsung,smdkv310" - for Exynos4210-based Samsung SMDKV310 eval board.
13 - "samsung,trats" - for Exynos4210-based Tizen Reference board.
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/Linux-v5.4/Documentation/powerpc/
Dultravisor.rst1 .. SPDX-License-Identifier: GPL-2.0
15 POWER 9 that enables Secure Virtual Machines (SVMs). DD2.3 chips
16 (PVR=0x004e1203) or greater will be PEF-capable. A new ISA release
25 +------------------+
29 +------------------+
31 +------------------+
33 +------------------+
35 +------------------+
56 process is running in secure mode, MSR(S) bit 41. MSR(S)=1, process
57 is in secure mode, MSR(s)=0 process is in normal mode.
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