Lines Matching +full:non +full:- +full:secure
13 (EL0 - EL3), with EL0 and EL1 having a secure and a non-secure
14 counterpart. EL2 is the hypervisor level and exists only in non-secure
15 mode. EL3 is the highest priority level and exists only in secure mode.
19 is passed to the Linux kernel. This may include secure monitor and
33 ---------------------------
46 -------------------------
50 The device tree blob (dtb) must be placed on an 8-byte boundary and must
59 ------------------------------
71 ------------------------
75 The decompressed kernel image contains a 64-byte header as follows::
91 - As of v3.17, all fields are little endian unless stated otherwise.
93 - code0/code1 are responsible for branching to stext.
95 - when booting through EFI, code0/code1 are initially skipped.
100 - Prior to v3.17, the endianness of text_offset was not specified. In
102 endianness of the kernel. Where image_size is non-zero image_size is
103 little-endian and must be respected. Where image_size is zero,
106 - The flags field (introduced in v3.17) is a little-endian 64-bit field
111 Bit 1-2 Kernel Page size.
113 * 0 - Unspecified.
114 * 1 - 4K
115 * 2 - 16K
116 * 3 - 64K
126 Bits 4-63 Reserved.
129 - When image_size is zero, a bootloader should attempt to keep as much
155 - Quiesce all DMA capable devices so that memory does not get
159 - Primary CPU general-purpose register settings:
161 - x0 = physical address of device tree blob (dtb) in system RAM.
162 - x1 = 0 (reserved for future use)
163 - x2 = 0 (reserved for future use)
164 - x3 = 0 (reserved for future use)
166 - CPU mode
171 the virtualisation extensions) or non-secure EL1.
173 - Caches, MMUs
186 - Architected timers
193 - Coherency
200 - System registers
206 - SCR_EL3.FIQ must have the same value across all CPUs the kernel is
208 - The value of SCR_EL3.FIQ must be the same as the one present at boot
212 - If EL3 is present:
214 - ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.
215 - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
217 - If the kernel is entered at EL1:
219 - ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
220 - ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
222 - The DT or ACPI tables must describe a GICv3 interrupt controller.
227 - If EL3 is present:
231 - If the kernel is entered at EL1:
235 - The DT or ACPI tables must describe a GICv2 interrupt controller.
238 - If EL3 is present:
240 - SCR_EL3.APK (bit 16) must be initialised to 0b1
241 - SCR_EL3.API (bit 17) must be initialised to 0b1
243 - If the kernel is entered at EL1:
245 - HCR_EL2.APK (bit 40) must be initialised to 0b1
246 - HCR_EL2.API (bit 41) must be initialised to 0b1
255 - The primary CPU must jump directly to the first instruction of the
257 an 'enable-method' property for each cpu node. The supported
258 enable-methods are described below.
263 - CPUs with a "spin-table" enable-method must have a 'cpu-release-addr'
265 naturally-aligned 64-bit zero-initalised memory location.
269 device tree) polling their cpu-release-addr location, which must be
271 to reduce the overhead of the busy-loop and a sev will be issued by
273 cpu-release-addr returns a non-zero value, the CPU must jump to this
274 value. The value will be written as a single 64-bit little-endian
278 - CPUs with a "psci" enable method should remain outside of
289 - Secondary CPU general-purpose register settings