| /Linux-v5.10/drivers/pci/controller/ |
| D | pcie-iproc-msi.c | 9 #include <linux/msi.h>
34 /* Size of each MSI address region */
52 * iProc MSI group
54 * One MSI group is allocated per GIC interrupt, serviced by one iProc MSI
57 * @msi: pointer to iProc MSI data
62 struct iproc_msi *msi; member
68 * iProc event queue based MSI
70 * Only meant to be used on platforms without MSI support integrated into the
74 * @reg_offsets: MSI register offsets
75 * @grps: MSI groups
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| D | pcie-altera-msi.c | 3 * Altera PCIe MSI support
14 #include <linux/msi.h>
41 static inline void msi_writel(struct altera_msi *msi, const u32 value, in msi_writel() argument
44 writel_relaxed(value, msi->csr_base + reg); in msi_writel()
47 static inline u32 msi_readl(struct altera_msi *msi, const u32 reg) in msi_readl() argument
49 return readl_relaxed(msi->csr_base + reg); in msi_readl()
55 struct altera_msi *msi; in altera_msi_isr() local
61 msi = irq_desc_get_handler_data(desc); in altera_msi_isr()
63 while ((status = msi_readl(msi, MSI_STATUS)) != 0) { in altera_msi_isr()
64 for_each_set_bit(bit, &status, msi->num_of_vectors) { in altera_msi_isr()
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| D | pci-xgene-msi.c | 3 * APM X-Gene MSI Driver
12 #include <linux/msi.h>
27 struct xgene_msi *msi; member
48 .name = "X-Gene1 MSI",
62 * X-Gene v1 has 16 groups of MSI termination registers MSInIRx, where
85 * Each index register supports 16 MSI vectors (0..15) to generate interrupt.
86 * There are total 16 GIC IRQs assigned for these 16 groups of MSI termination
89 * Each MSI termination group has 1 MSIINTn register (n is 0..15) to indicate
90 * the MSI pending status caused by 1 of its 8 index registers.
94 static u32 xgene_msi_ir_read(struct xgene_msi *msi, in xgene_msi_ir_read() argument
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| D | pcie-brcmstb.c | 19 #include <linux/msi.h>
150 /* MSI target adresses */
262 /* used indicates which MSI interrupts have been alloc'd */
267 int nr; /* No. of MSI available, depends on chip */
281 struct brcm_msi *msi; member
456 .name = "BRCM STB PCIe MSI",
463 /* Multi MSI is supported by the controller, but not by this driver */
472 struct brcm_msi *msi; in brcm_pcie_msi_isr() local
477 msi = irq_desc_get_handler_data(desc); in brcm_pcie_msi_isr()
478 dev = msi->dev; in brcm_pcie_msi_isr()
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| D | pcie-rcar-host.c | 22 #include <linux/msi.h>
57 struct rcar_msi msi; member
298 bridge->msi = &host->msi.chip; in rcar_pcie_enable()
394 /* Enable MSI */ in rcar_pcie_hw_init()
480 int msi; in rcar_msi_alloc() local
484 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR); in rcar_msi_alloc()
485 if (msi < INT_PCI_MSI_NR) in rcar_msi_alloc()
486 set_bit(msi, chip->used); in rcar_msi_alloc()
488 msi = -ENOSPC; in rcar_msi_alloc()
492 return msi; in rcar_msi_alloc()
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| /Linux-v5.10/Documentation/devicetree/bindings/pci/ |
| D | pci-msi.txt | 2 relationship between PCI devices and MSI controllers.
18 Requester ID. A mechanism is required to associate a device with both the MSI
22 For generic MSI bindings, see
23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
32 - msi-map: Maps a Requester ID to an MSI controller and associated
33 msi-specifier data. The property is an arbitrary number of tuples of
34 (rid-base,msi-controller,msi-base,length), where:
38 * msi-controller is a single phandle to an MSI controller
40 * msi-base is an msi-specifier describing the msi-specifier produced for the
47 the listed msi-controller, with the msi-specifier (r - rid-base + msi-base).
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| D | brcm,iproc-pcie.txt | 44 MSI support (optional):
46 For older platforms without MSI integrated in the GIC, iProc PCIe core provides
47 an event queue based MSI support. The iProc MSI uses host memories to store
48 MSI posted writes in the event queues
50 On newer iProc platforms, gicv2m or gicv3-its based MSI support should be used
52 - msi-map: Maps a Requester ID to an MSI controller and associated MSI
55 - msi-parent: Link to the device node of the MSI controller, used when no MSI
56 sideband data is passed between the iProc PCIe controller and the MSI
60 the use of 'msi-map' and 'msi-parent':
61 Documentation/devicetree/bindings/pci/pci-msi.txt
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| D | xgene-pci-msi.txt | 1 * AppliedMicro X-Gene v1 PCIe MSI controller
5 - compatible: should be "apm,xgene1-msi" to identify
6 X-Gene v1 PCIe MSI controller block.
7 - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
9 registers. These registers include the MSI termination address and data
10 registers as well as the MSI interrupt status registers.
16 Each PCIe node needs to have property msi-parent that points to an MSI
23 + MSI node:
24 msi@79000000 {
25 compatible = "apm,xgene1-msi";
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| /Linux-v5.10/arch/powerpc/platforms/4xx/ |
| D | msi.c | 3 * Adding PCI-E MSI support for PPC4XX SoCs.
12 #include <linux/msi.h>
73 dev_dbg(&dev->dev, "PCIE-MSI:%s called. vec %x type %d\n", in ppc4xx_setup_msi_irqs()
76 pr_debug("ppc4xx msi: MSI-X untested, trying anyway.\n"); in ppc4xx_setup_msi_irqs()
87 pr_debug("%s: fail allocating msi interrupt\n", in ppc4xx_setup_msi_irqs()
98 /* Setup msi address space */ in ppc4xx_setup_msi_irqs()
115 dev_dbg(&dev->dev, "PCIE-MSI: tearing down msi irqs\n"); in ppc4xx_teardown_msi_irqs()
128 struct resource res, struct ppc4xx_msi *msi) in ppc4xx_setup_pcieh_hw() argument
141 msi_data = of_get_property(dev->dev.of_node, "msi-data", NULL); in ppc4xx_setup_pcieh_hw()
145 msi_mask = of_get_property(dev->dev.of_node, "msi-mask", NULL); in ppc4xx_setup_pcieh_hw()
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| /Linux-v5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | msi.txt | 1 This document describes the generic device tree binding for MSI controllers and
9 those busses to the MSI controllers which they are capable of using,
17 they can address. An MSI controller may feature a number of doorbells.
22 MSI controllers may have restrictions on permitted payloads.
28 MSI controller and device rather than a property of either in isolation).
31 MSI controllers:
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
35 address by some master. An MSI controller may feature a number of doorbells.
40 - msi-controller: Identifies the node as an MSI controller.
45 - #msi-cells: The number of cells in an msi-specifier, required if not zero.
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| D | loongson,pch-msi.yaml | 4 $id: "http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#"
7 title: Loongson PCH MSI Controller
14 transforming interrupts from PCIe MSI into HyperTransport vectorized
19 const: loongson,pch-msi-1.0
24 loongson,msi-base-vec:
27 to PCH MSI.
32 loongson,msi-num-vecs:
35 to PCH MSI.
40 msi-controller: true
45 - msi-controller
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| D | fsl,ls-scfg-msi.txt | 1 * Freescale Layerscape SCFG PCIe MSI controller
5 - compatible: should be "fsl,<soc-name>-msi" to identify
6 Layerscape PCIe MSI controller block such as:
7 "fsl,ls1021a-msi"
8 "fsl,ls1043a-msi"
9 "fsl,ls1046a-msi"
10 "fsl,ls1043a-v1.1-msi"
11 "fsl,ls1012a-msi"
12 - msi-controller: indicates that this is a PCIe MSI controller node
20 Each PCIe node needs to have property msi-parent that points to
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| D | arm,gic-v3.yaml | 105 msi-controller:
149 mbi-ranges: [ msi-controller ]
150 msi-controller: [ mbi-ranges ]
160 # msi-controller is preferred, but allow other names
161 "^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$":
165 used to route Message Signalled Interrupts (MSI) to the CPUs.
170 msi-controller: true
172 "#msi-cells":
174 The single msi-cell is the DeviceID of the device which will generate
175 the MSI.
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| /Linux-v5.10/arch/powerpc/sysdev/ |
| D | fsl_msi.c | 11 #include <linux/msi.h>
35 #define msi_hwirq(msi, msir_index, intr_index) \ argument
36 ((msir_index) << (msi)->srs_shift | \
37 ((intr_index) << (msi)->ibs_shift))
59 * in the cascade interrupt. So, this MSI interrupt has been acked
74 seq_printf(p, " fsl-msi-%d", cascade_virq); in fsl_msi_print_chip()
151 /* If the msi-address-64 property exists, then use it */ in fsl_compose_msi_msg()
152 reg = of_get_property(hose->dn, "msi-address-64", &len); in fsl_compose_msi_msg()
163 * that neither MSI nor MSI-X can work fine. in fsl_compose_msi_msg()
164 * This is a workaround to allow MSI-X to function in fsl_compose_msi_msg()
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| /Linux-v5.10/arch/arm64/kvm/vgic/ |
| D | vgic-irqfd.c | 55 e->msi.address_lo = ue->u.msi.address_lo; in kvm_set_routing_entry()
56 e->msi.address_hi = ue->u.msi.address_hi; in kvm_set_routing_entry()
57 e->msi.data = ue->u.msi.data; in kvm_set_routing_entry()
58 e->msi.flags = ue->flags; in kvm_set_routing_entry()
59 e->msi.devid = ue->u.msi.devid; in kvm_set_routing_entry()
70 struct kvm_msi *msi) in kvm_populate_msi() argument
72 msi->address_lo = e->msi.address_lo; in kvm_populate_msi()
73 msi->address_hi = e->msi.address_hi; in kvm_populate_msi()
74 msi->data = e->msi.data; in kvm_populate_msi()
75 msi->flags = e->msi.flags; in kvm_populate_msi()
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| /Linux-v5.10/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | msi-pic.txt | 1 * Freescale MSI interrupt controller
5 The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
6 etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or
7 "fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic
8 version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is
9 provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3"
17 region must be added because different MSI group has different MSIIR1 offset.
21 be set as edge sensitive. If msi-available-ranges is present, only
25 - msi-available-ranges: use <start count> style section to define which
26 msi interrupt can be used in the 256 msi interrupts. This property is
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| /Linux-v5.10/Documentation/PCI/ |
| D | msi-howto.rst | 5 The MSI Driver Guide HOWTO
16 the advantages of using MSI over traditional interrupt mechanisms, how
17 to change your driver to use MSI or MSI-X and some basic diagnostics to
27 The MSI capability was first specified in PCI 2.2 and was later enhanced
28 in PCI 3.0 to allow each interrupt to be masked individually. The MSI-X
30 per device than MSI and allows interrupts to be independently configured.
32 Devices may support both MSI and MSI-X, but only one can be enabled at
73 driver has to set up the device to use MSI or MSI-X. Not all machines
80 To support MSI or MSI-X, the kernel must be built with the CONFIG_PCI_MSI
86 Using MSI
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| /Linux-v5.10/arch/mips/pci/ |
| D | msi-xlp.c | 39 #include <linux/msi.h>
62 /* 128 MSI irqs per node, mapped starting at NLM_MSI_VEC_BASE */
68 /* get the link MSI vector from irq number */
84 * For XLP 8xx/4xx/3xx/2xx, only 32 MSI-X vectors are possible because
85 * there are only 32 PIC interrupts for MSI. We split them statically
86 * and use 8 MSI-X vectors per link - this keeps the allocation and
89 * not routed thru PIC, so we can use all 128 MSI-X vectors.
96 /* get the link MSI vector from irq number */
109 * Per link MSI and MSI-X information, set as IRQ handler data for
110 * MSI and MSI-X interrupts.
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| D | msi-octeon.c | 10 #include <linux/msi.h>
23 * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
31 * is used so we can disable all of the MSI interrupts when a device
43 * Number of MSI IRQs used. This variable is set up in
49 * Called when a driver request MSI interrupts instead of the
51 * for MSI devices that support them. A device can override this by
52 * programming the MSI control bits [6:4] before calling
55 * @dev: Device requesting MSI interrupts
56 * @desc: MSI descriptor
72 * Read the MSI config to figure out how many IRQs this device in arch_setup_msi_irq()
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| /Linux-v5.10/drivers/pci/controller/mobiveil/ |
| D | pcie-mobiveil-host.c | 19 #include <linux/msi.h>
91 struct mobiveil_msi *msi = &rp->msi; in mobiveil_pcie_isr() local
98 * The core provides a single interrupt for both INTx/MSI messages. in mobiveil_pcie_isr()
99 * So we'll read both INTx and MSI status in mobiveil_pcie_isr()
138 /* read extra MSI status register */ in mobiveil_pcie_isr()
141 /* handle MSI interrupts */ in mobiveil_pcie_isr()
147 * once we pop not only the MSI data but also address in mobiveil_pcie_isr()
148 * from MSI hardware FIFO. So keeping these following in mobiveil_pcie_isr()
155 dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n", in mobiveil_pcie_isr()
158 virq = irq_find_mapping(msi->dev_domain, msi_data); in mobiveil_pcie_isr()
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| /Linux-v5.10/include/linux/ |
| D | msi.h | 9 u32 address_lo; /* low 32 bits of msi message address */
10 u32 address_hi; /* high 32 bits of msi message address */
11 u32 data; /* 16 bits of msi message data */
33 * platform_msi_desc - Platform device specific msi descriptor data
35 * @msi_index: The index of the MSI descriptor for multi MSI
43 * fsl_mc_msi_desc - FSL-MC device specific msi descriptor data
44 * @msi_index: The index of the MSI descriptor
51 * ti_sci_inta_msi_desc - TISCI based INTA specific msi descriptor data
59 * struct msi_desc - Descriptor structure for MSI based interrupts
64 * @msg: The last set MSI message cached for reuse
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| /Linux-v5.10/drivers/ntb/ |
| D | msi.c | 6 #include <linux/msi.h>
19 * ntb_msi_init() - Initialize the MSI context
23 * It initializes the context for MSI operations and maps
46 struct_size = sizeof(*ntb->msi) + sizeof(*ntb->msi->peer_mws) * peers; in ntb_msi_init()
48 ntb->msi = devm_kzalloc(&ntb->dev, struct_size, GFP_KERNEL); in ntb_msi_init()
49 if (!ntb->msi) in ntb_msi_init()
52 ntb->msi->desc_changed = desc_changed; in ntb_msi_init()
62 ntb->msi->peer_mws[i] = devm_ioremap(&ntb->dev, mw_phys_addr, in ntb_msi_init()
64 if (!ntb->msi->peer_mws[i]) { in ntb_msi_init()
74 if (ntb->msi->peer_mws[i]) in ntb_msi_init()
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| /Linux-v5.10/Documentation/PCI/endpoint/ |
| D | pci-test-howto.rst | 79 to change the vendorid and the number of MSI interrupts used by the function
158 SET IRQ TYPE TO MSI: OKAY
191 SET IRQ TYPE TO MSI-X: OKAY
192 MSI-X1: OKAY
193 MSI-X2: OKAY
194 MSI-X3: OKAY
195 MSI-X4: OKAY
196 MSI-X5: OKAY
197 MSI-X6: OKAY
198 MSI-X7: OKAY
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| /Linux-v5.10/drivers/pci/ |
| D | msi.c | 3 * PCI Message Signaled Interrupt (MSI)
18 #include <linux/msi.h>
65 struct msi_controller *chip = dev->bus->msi; in arch_setup_msi_irq()
92 struct msi_controller *chip = dev->bus->msi; in arch_setup_msi_irqs()
99 * If an architecture wants to support multiple MSI, it needs to in arch_setup_msi_irqs()
169 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
170 * mask all MSI interrupts by clearing the MSI enable bit does not work
208 * of MSI-X interrupts.
250 * pci_msi_mask_irq - Generic IRQ chip callback to mask PCI/MSI interrupts
260 * pci_msi_unmask_irq - Generic IRQ chip callback to unmask PCI/MSI interrupts
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| /Linux-v5.10/arch/sparc/kernel/ |
| D | pci_msi.c | 2 /* pci_msi.c: Sparc64 MSI support common layer.
30 unsigned long msi; in sparc64_msiq_interrupt() local
32 err = ops->dequeue_msi(pbm, msiqid, &head, &msi); in sparc64_msiq_interrupt()
36 irq = pbm->msi_irq_table[msi - pbm->msi_first]; in sparc64_msiq_interrupt()
54 printk(KERN_EMERG "MSI: Get head on msiqid[%lu] gives error %d\n", in sparc64_msiq_interrupt()
59 printk(KERN_EMERG "MSI: Dequeue head[%lu] from msiqid[%lu] " in sparc64_msiq_interrupt()
65 printk(KERN_EMERG "MSI: Set head[%lu] on msiqid[%lu] " in sparc64_msiq_interrupt()
114 .name = "PCI-MSI",
129 int msi, err; in sparc64_setup_msi_irq() local
138 "MSI"); in sparc64_setup_msi_irq()
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