| /Linux-v6.1/drivers/gpu/drm/msm/adreno/ |
| D | a6xx_gmu.c | 17 static void a6xx_gmu_fault(struct a6xx_gmu *gmu) in a6xx_gmu_fault() argument
19 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); in a6xx_gmu_fault()
24 gmu->hung = true; in a6xx_gmu_fault()
35 struct a6xx_gmu *gmu = data; in a6xx_gmu_irq() local
38 status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS); in a6xx_gmu_irq()
39 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status); in a6xx_gmu_irq()
42 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n"); in a6xx_gmu_irq()
44 a6xx_gmu_fault(gmu); in a6xx_gmu_irq()
48 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n"); in a6xx_gmu_irq()
51 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n", in a6xx_gmu_irq()
[all …]
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| D | a6xx_gmu.h | 20 * These define the different GMU wake up options - these define how both the
21 * CPU and the GMU bring up the hardware
24 /* THe GMU has already been booted and the rentention registers are active */
27 /* the GMU is coming up for the first time or back from a power collapse */
31 * These define the level of control that the GMU has - the higher the number
32 * the more things that the GMU hardware controls on its own.
35 /* The GMU does not do any idle state management */
38 /* The GMU manages SPTP power collapse */
41 /* The GMU does automatic IFPC (intra-frame power collapse) */
47 /* For serializing communication with the GMU: */
[all …]
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| D | a6xx_hfi.c | 26 static int a6xx_hfi_queue_read(struct a6xx_gmu *gmu, in a6xx_hfi_queue_read() argument
42 * If we are to assume that the GMU firmware is in fact a rational actor in a6xx_hfi_queue_read()
57 if (!gmu->legacy) in a6xx_hfi_queue_read()
64 static int a6xx_hfi_queue_write(struct a6xx_gmu *gmu, in a6xx_hfi_queue_write() argument
88 if (!gmu->legacy) { in a6xx_hfi_queue_write()
96 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 0x01); in a6xx_hfi_queue_write()
100 static int a6xx_hfi_wait_for_ack(struct a6xx_gmu *gmu, u32 id, u32 seqnum, in a6xx_hfi_wait_for_ack() argument
103 struct a6xx_hfi_queue *queue = &gmu->queues[HFI_RESPONSE_QUEUE]; in a6xx_hfi_wait_for_ack()
108 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val, in a6xx_hfi_wait_for_ack()
112 DRM_DEV_ERROR(gmu->dev, in a6xx_hfi_wait_for_ack()
[all …]
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| D | a6xx_gpu.h | 23 struct a6xx_gmu gmu; member
70 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu);
72 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu);
74 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
75 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
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| D | a6xx_gpu_state.c | 144 if (!a6xx_gmu_sptprac_is_on(&a6xx_gpu->gmu)) in a6xx_crashdumper_run()
743 /* Read a block of GMU registers */
752 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in _a6xx_get_gmu_registers() local
772 val = gmu_read_rscc(gmu, offset); in _a6xx_get_gmu_registers()
774 val = gmu_read(gmu, offset); in _a6xx_get_gmu_registers()
795 /* Get the CX GMU registers from AHB */ in a6xx_get_gmu_registers()
801 if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) in a6xx_get_gmu_registers()
839 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_snapshot_gmu_hfi_history() local
842 BUILD_BUG_ON(ARRAY_SIZE(gmu->queues) != ARRAY_SIZE(a6xx_state->hfi_queue_history)); in a6xx_snapshot_gmu_hfi_history()
844 for (i = 0; i < ARRAY_SIZE(gmu->queues); i++) { in a6xx_snapshot_gmu_hfi_history()
[all …]
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| D | a6xx_gpu.c | 23 /* Check that the GMU is idle */ in _a6xx_check_idle()
24 if (!a6xx_gmu_isidle(&a6xx_gpu->gmu)) in _a6xx_check_idle()
186 * For PM4 the GMU register offsets are calculated from the base of the in a6xx_submit()
596 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_set_hwcg() local
616 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); in a6xx_set_hwcg()
622 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); in a6xx_set_hwcg()
988 /* Make sure the GMU keeps the GPU on while we set it up */ in hw_init()
989 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); in hw_init()
1229 * Tell the GMU that we are done touching the GPU and it can start power in hw_init()
1232 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); in hw_init()
[all …]
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| D | a6xx_hfi.h | 49 /* This is the outgoing queue to the GMU */
52 /* THis is the incoming response queue from the GMU */
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| D | a6xx_gpu_state.h | 325 /* GMU GX */
334 /* GMU CX */
344 /* GMU AO */
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| /Linux-v6.1/Documentation/devicetree/bindings/display/msm/ |
| D | gmu.yaml | 6 $id: "http://devicetree.org/schemas/display/msm/gmu.yaml#"
9 title: Devicetree bindings for the GMU attached to certain Adreno GPUs
15 These bindings describe the Graphics Management Unit (GMU) that is attached
16 to members of the Adreno A6xx GPU family. The GMU provides on-device power
23 - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$'
24 - const: qcom,adreno-gmu
44 - description: GMU HFI interrupt
45 - description: GMU interrupt
51 - const: gmu
92 - qcom,adreno-gmu-618.0
[all …]
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| D | gpu.yaml | 108 qcom,gmu:
111 For GMU attached devices a phandle to the GMU device that will
164 then: # Since Adreno 6xx series clocks should be defined in GMU
221 // Example a6xx (with GMU):
258 qcom,gmu = <&gmu>;
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| /Linux-v6.1/arch/arm64/boot/dts/qcom/ |
| D | msm8992.dtsi | 30 gmu-sram@0 {
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| D | sc7180.dtsi | 1956 qcom,gmu = <&gmu>;
2050 gmu: gmu@506a000 { label
2051 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2054 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2057 interrupt-names = "hfi", "gmu";
2062 clock-names = "gmu", "cxo", "axi", "memnoc";
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| D | sm8150.dtsi | 2145 qcom,gmu = <&gmu>;
2189 gmu: gmu@2c6a000 { label
2190 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2195 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2199 interrupt-names = "hfi", "gmu";
2206 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
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| D | sm8150-hdk.dts | 357 &gmu {
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| D | sm8150-mtp.dts | 352 &gmu {
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| D | sdm845.dtsi | 4677 * controlled entirely by the GMU
4686 qcom,gmu = <&gmu>;
4762 gmu: gmu@506a000 { label
4763 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4768 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4772 interrupt-names = "hfi", "gmu";
4778 clock-names = "gmu", "cxo", "axi", "memnoc";
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| D | sm8250-hdk.dts | 367 &gmu {
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| D | sc7280.dtsi | 2531 qcom,gmu = <&gmu>;
2608 gmu: gmu@3d6a000 { label
2609 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
2613 reg-names = "gmu", "rscc", "gmu_pdc";
2616 interrupt-names = "hfi", "gmu";
2624 clock-names = "gmu",
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| D | sm8250.dtsi | 2539 qcom,gmu = <&gmu>;
2588 gmu: gmu@3d6a000 { label
2589 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2595 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2599 interrupt-names = "hfi", "gmu";
2606 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
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| D | sdm845-xiaomi-beryllium.dts | 263 &gmu {
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| D | sdm845-oneplus-common.dtsi | 366 &gmu {
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| D | sdm845-shift-axolotl.dts | 459 &gmu {
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| D | sdm850-lenovo-yoga-c630.dts | 340 &gmu {
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| /Linux-v6.1/Documentation/devicetree/bindings/sram/ |
| D | qcom,ocmem.yaml | 95 gmu-sram@0 {
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| /Linux-v6.1/drivers/clk/qcom/ |
| D | gdsc.c | 538 * On SDM845+ the GPU GX domain is *almost* entirely controlled by the GMU
543 * the GMU crashes it could leave the GX on. In order to successfully bring back
552 * driver. During power up, nothing will happen from the CPU (and the GMU will
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