20  * These define the different GMU wake up options - these define how both the
21  * CPU and the GMU bring up the hardware
24 /* THe GMU has already been booted and the rentention registers are active */
27 /* the GMU is coming up for the first time or back from a power collapse */
31  * These define the level of control that the GMU has - the higher the number
32  * the more things that the GMU hardware controls on its own.
35 /* The GMU does not do any idle state management */
38 /* The GMU manages SPTP power collapse */
41 /* The GMU does automatic IFPC (intra-frame power collapse) */
47 	/* For serializing communication with the GMU: */
94 static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset)  in gmu_read()  argument
96 	return msm_readl(gmu->mmio + (offset << 2));  in gmu_read()
99 static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value)  in gmu_write()  argument
101 	msm_writel(value, gmu->mmio + (offset << 2));  in gmu_write()
105 gmu_write_bulk(struct a6xx_gmu *gmu, u32 offset, const u32 *data, u32 size)  in gmu_write_bulk()  argument
107 	memcpy_toio(gmu->mmio + (offset << 2), data, size);  in gmu_write_bulk()
111 static inline void gmu_rmw(struct a6xx_gmu *gmu, u32 reg, u32 mask, u32 or)  in gmu_rmw()  argument
113 	u32 val = gmu_read(gmu, reg);  in gmu_rmw()
117 	gmu_write(gmu, reg, val | or);  in gmu_rmw()
120 static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi)  in gmu_read64()  argument
124 	val = (u64) msm_readl(gmu->mmio + (lo << 2));  in gmu_read64()
125 	val |= ((u64) msm_readl(gmu->mmio + (hi << 2)) << 32);  in gmu_read64()
130 #define gmu_poll_timeout(gmu, addr, val, cond, interval, timeout) \  argument
131 	readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \
134 static inline u32 gmu_read_rscc(struct a6xx_gmu *gmu, u32 offset)  in gmu_read_rscc()  argument
136 	return msm_readl(gmu->rscc + (offset << 2));  in gmu_read_rscc()
139 static inline void gmu_write_rscc(struct a6xx_gmu *gmu, u32 offset, u32 value)  in gmu_write_rscc()  argument
141 	msm_writel(value, gmu->rscc + (offset << 2));  in gmu_write_rscc()
144 #define gmu_poll_timeout_rscc(gmu, addr, val, cond, interval, timeout) \  argument
145 	readl_poll_timeout((gmu)->rscc + ((addr) << 2), val, cond, \
149  * These are the available OOB (out of band requests) to the GMU where "out of
150  * band" means that the CPU talks to the GMU directly and not through HFI.
153  * bit). The state is cleared by writing the "clear' bit to the GMU interrupt.
155  * These are used to force the GMU/GPU to stay on during a critical sequence or
161 	 * Let the GMU know that a boot or slumber operation has started. The value in
162 	 * REG_A6XX_GMU_BOOT_SLUMBER_OPTION lets the GMU know which operation we are
167 	 * Let the GMU know to not turn off any GPU registers while the CPU is in a
181 void a6xx_hfi_init(struct a6xx_gmu *gmu);
182 int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state);
183 void a6xx_hfi_stop(struct a6xx_gmu *gmu);
184 int a6xx_hfi_send_prep_slumber(struct a6xx_gmu *gmu);
185 int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, int index);
187 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu);
188 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu);