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/Linux-v6.1/Documentation/devicetree/bindings/interrupt-controller/
Dapple,aic2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
18 - Level-triggered hardware IRQs wired to SoC blocks
19 - Single mask bit per IRQ
20 - Automatic masking on event delivery (auto-ack)
21 - Software triggering (ORed with hw line)
22 - Automatic prioritization (single event/ack register per CPU, lower IRQs =
[all …]
Dst,sti-irq-syscfg.txt2 -----------------------------------------------------------
4 On STi based systems; External, CTI (Core Sight), PMU (Performance Management),
9 - compatible : Should be set to one of:
10 "st,stih415-irq-syscfg"
11 "st,stih416-irq-syscfg"
12 "st,stih407-irq-syscfg"
13 "st,stid127-irq-syscfg"
14 - st,syscfg : Phandle to Cortex-A9 IRQ system config registers
15 - st,irq-device : Array of IRQs to enable - should be 2 in length
16 - st,fiq-device : Array of FIQs to enable - should be 2 in length
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/Linux-v6.1/arch/arm/mach-omap1/
Dams-delta-fiq-handler.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mach-omap1/ams-delta-fiq-handler.S
5 * Based on linux/arch/arm/lib/floppydma.S
14 #include <linux/platform_data/ams-delta-fiq.h>
15 #include <linux/platform_data/gpio-omap.h>
16 #include <linux/soc/ti/omap1-io.h>
22 #include "ams-delta-fiq.h"
23 #include "board-ams-delta.h"
27 * OMAP1510 GPIO related symbol copied from arch/arm/mach-omap1/gpio15xx.c.
79 * r8 - temporary
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
23 bool "OMAP730 Based System"
30 bool "OMAP850 Based System"
37 bool "OMAP15xx Based System"
43 bool "OMAP16xx Based System"
90 intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
103 timer provides more intra-tick resolution than the 32KHz timer,
107 bool "Enable wake-up events for serial ports"
161 HTC Herald smartphone support (AKA T-Mobile Wing, ...)
175 The OSK supports an optional add-on board with a Quarter-VGA
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Dboard-ams-delta.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-omap1/board-ams-delta.c
5 * Modified from board-generic.c
20 #include <linux/mtd/nand-gpio.h>
30 #include <linux/platform_data/gpio-omap.h>
31 #include <linux/soc/ti/omap1-mux.h>
34 #include <asm/mach-types.h>
38 #include <linux/platform_data/keypad-omap.h>
42 #include "ams-delta-fiq.h"
43 #include "board-ams-delta.h"
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/Linux-v6.1/drivers/spi/
Dspi-s3c24xx.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2009 Simtec Electronics
21 #include <linux/spi/s3c24xx-fiq.h>
24 #include <asm/fiq.h>
26 #include "spi-s3c24xx-regs.h"
29 * struct s3c24xx_spi_devstate - per device data
80 return spi_master_get_devdata(sdev->master); in to_hw()
85 struct s3c24xx_spi_devstate *cs = spi->controller_state; in s3c24xx_spi_chipsel()
92 writeb(cs->spcon, hw->regs + S3C2410_SPCON); in s3c24xx_spi_chipsel()
96 writeb(cs->spcon | S3C2410_SPCON_ENSCK, in s3c24xx_spi_chipsel()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
138 supports spi-mem interface.
199 based platforms. This driver works for both SPI master for SPI NOR
208 this code to manage the per-word or per-transfer accesses to the
238 Flash over 1/2/4-bit wide bus. Enable this option if you have a
258 This enables dedicated general purpose SPI/Microwire1-compatible
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/Linux-v6.1/drivers/irqchip/
Dirq-ixp4xx.c1 // SPDX-License-Identifier: GPL-2.0
6 * Based on arch/arm/mach-ixp4xx/common.c
8 * Copyright 2003-2004 (C) MontaVista, Software, Inc.
28 #define IXP4XX_ICLR 0x08 /* Interrupt IRQ/FIQ Select */
30 #define IXP4XX_ICFP 0x10 /* FIQ Status */
33 #define IXP4XX_ICFH 0x1C /* FIQ Highest Pri Int */
35 /* IXP43x and IXP46x-only */
38 #define IXP4XX_ICLR2 0x28 /* Interrupt IRQ/FIQ Select 2 */
40 #define IXP4XX_ICFP2 0x30 /* FIQ Status */
44 * struct ixp4xx_irq - state container for the Faraday IRQ controller
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Dirq-apple-aic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Based on irq-lpc32xx:
6 * Copyright 2015-2016 Vladimir Zapolskiy <vz@mleia.com>
7 * Based on irq-bcm2836:
14 * - 896 level-triggered hardware IRQs
15 * - Single mask bit per IRQ
16 * - Per-IRQ affinity setting
17 * - Automatic masking on event delivery (auto-ack)
18 * - Software triggering (ORed with hw line)
19 * - 2 per-CPU IPIs (meant as "self" and "other", but they are
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Dirq-sa11x0.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Dmitry Eremin-Solenikov
4 * Copyright (C) 1999-2001 Nicolas Pitre
15 #include <linux/irqchip/irq-sa11x0.h>
25 #define ICFP 0x10 /* IC FIQ Pending reg. */
39 reg &= ~BIT(d->hwirq); in sa1100_mask_irq()
48 reg |= BIT(d->hwirq); in sa1100_unmask_irq()
54 return sa11x0_sc_set_wake(d->hwirq, on); in sa1100_set_wake()
92 st->saved = 1; in sa1100irq_suspend()
93 st->icmr = readl_relaxed(iobase + ICMR); in sa1100irq_suspend()
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/Linux-v6.1/arch/arm64/kernel/
Dirq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Based on arch/arm/kernel/irq.c
6 * Modifications for ARM processor Copyright (C) 1995-2000 Russell King.
7 * Support for Dynamic Tick Timer Copyright (C) 2004-2005 Nokia Corporation.
64 /* irq stack only needs to be 16 byte aligned - not IRQ_STACK_SIZE aligned. */
95 panic("FIQ taken without a root FIQ handler\n"); in default_handle_fiq()
104 return -EBUSY; in set_handle_irq()
114 return -EBUSY; in set_handle_fiq()
117 pr_info("Root FIQ handler: %ps\n", handle_fiq); in set_handle_fiq()
Dsetup.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Based on arch/arm/kernel/setup.c
5 * Copyright (C) 1995-2001 Russell King
102 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
112 * Pre-scan the list of MPIDRS and filter out bits that do in smp_build_mpidr_hash()
130 fs[i] = affinity ? ffs(affinity) - 1 : 0; in smp_build_mpidr_hash()
131 bits[i] = ls - fs[i]; in smp_build_mpidr_hash()
144 mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0]; in smp_build_mpidr_hash()
145 mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] - in smp_build_mpidr_hash()
148 fs[3] - (bits[2] + bits[1] + bits[0]); in smp_build_mpidr_hash()
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/Linux-v6.1/Documentation/devicetree/bindings/sound/
Dfsl,ssi.txt4 be programmed in AC97, I2S, left-justified, or right-justified modes.
7 - compatible: Compatible list, should contain one of the following
9 fsl,mpc8610-ssi
10 fsl,imx51-ssi
11 fsl,imx35-ssi
12 fsl,imx21-ssi
13 - cell-index: The SSI, <0> = SSI1, <1> = SSI2, and so on.
14 - reg: Offset and length of the register set for the device.
15 - interrupts: <a b> where a is the interrupt number and b is a
18 encoded based on the information in section 2)
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/Linux-v6.1/sound/soc/fsl/
Dimx-pcm-fiq.c1 // SPDX-License-Identifier: GPL-2.0+
2 // imx-pcm-fiq.c -- ALSA Soc Audio Layer
6 // This code is based on code copyrighted by Freescale,
12 #include <linux/dma-mapping.h>
26 #include <asm/fiq.h>
28 #include <linux/platform_data/asoc-imx-ssi.h>
30 #include "imx-ssi.h"
31 #include "imx-pcm.h"
48 struct snd_pcm_substream *substream = iprtd->substream; in snd_hrtimer_callback()
51 if (!atomic_read(&iprtd->playing) && !atomic_read(&iprtd->capturing)) in snd_hrtimer_callback()
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Dimx-pcm.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * This code is based on code copyrighted by Freescale,
12 #include <linux/dma/imx-dma.h>
15 * Do not change this as the FIQ handler depends on this size
35 return -ENODEV; in imx_pcm_dma_init()
47 return -ENODEV; in imx_pcm_fiq_init()
Dfsl_ssi.c1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
9 // Some notes why imx-pcm-fiq is used instead of DMA on some boards:
16 // we receive in our (PCM-) data stream. The only chance we have is to
17 // manually skip this data in the FIQ handler. With sampling rates different
19 // between pcm data and GPIO status data changes. Our FIQ handler is not
43 #include <linux/dma/imx-dma.h>
53 #include "imx-pcm.h"
55 /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */
66 * (bit-endianness must match byte-endianness). Processors typically write
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
14 This option is only useful for out-of-tree drivers since
15 in-tree drivers select it automatically.
26 This option is only useful for out-of-tree drivers since
27 in-tree drivers select it automatically.
36 This option is only useful for out-of-tree drivers since
37 in-tree drivers select it automatically.
54 This option is only useful for out-of-tree drivers since
55 in-tree drivers select it automatically.
67 This option is only useful for out-of-tree drivers since
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/Linux-v6.1/fs/fuse/
Dfuse_i.h3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
23 #include <linux/backing-dev.h>
41 /** Bias for fi->writectr, meaning new writepages must not be sent */
87 /** The sticky bit in inode->i_mode may have been removed, so
100 /* Files usable in writepage. Protected by fi->lock */
221 /** RB node to be linked on fuse_conn->polled_files */
337 * - FR_ABORTED
338 * - FR_LOCKED (may also be modified under fc->lock, tested under both)
371 /** virtio-fs's physically contiguous buffer for in and out args */
384 * Input queue signalling is device-specific. For example, the /dev/fuse file
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Dinode.c3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
79 fi->i_time = 0; in fuse_alloc_inode()
80 fi->inval_mask = 0; in fuse_alloc_inode()
81 fi->nodeid = 0; in fuse_alloc_inode()
82 fi->nlookup = 0; in fuse_alloc_inode()
83 fi->attr_version = 0; in fuse_alloc_inode()
84 fi->orig_ino = 0; in fuse_alloc_inode()
85 fi->state = 0; in fuse_alloc_inode()
86 mutex_init(&fi->mutex); in fuse_alloc_inode()
87 spin_lock_init(&fi->lock); in fuse_alloc_inode()
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/Linux-v6.1/Documentation/arm64/
Dbooting.rst9 This document is based on the ARM booting document by Russell King and
13 (EL0 - EL3), with EL0, EL1 and EL2 having a secure and a non-secure
33 ---------------------------
46 -------------------------
50 The device tree blob (dtb) must be placed on an 8-byte boundary and must
59 ------------------------------
71 ------------------------
75 The decompressed kernel image contains a 64-byte header as follows::
91 - As of v3.17, all fields are little endian unless stated otherwise.
93 - code0/code1 are responsible for branching to stext.
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/Linux-v6.1/arch/arm64/kvm/hyp/
Dexception.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012,2013 - ARM Ltd
8 * Based on arch/arm/kvm/emulate.c
9 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
53 vcpu->arch.ctxt.spsr_abt = val; in __vcpu_write_spsr_abt()
61 vcpu->arch.ctxt.spsr_und = val; in __vcpu_write_spsr_und()
67 * The EL passed to this function *must* be a non-secure, privileged mode with
75 * For the SPSR_ELx layout for AArch64, see ARM DDI 0487E.a page C5-429.
76 * For the SPSR_ELx layout for AArch32, see ARM DDI 0487E.a page C5-426.
119 if (kvm_has_mte(kern_hyp_va(vcpu->kvm))) in enter_exception64()
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/Linux-v6.1/arch/arm/include/asm/
Dptrace.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1996-2003 Russell King
27 (((regs)->ARM_cpsr & 0xf) == 0)
31 (((regs)->ARM_cpsr & PSR_T_BIT))
38 ((((regs)->ARM_cpsr & PSR_J_BIT) >> (__ffs(PSR_J_BIT) - 1)) | \
39 (((regs)->ARM_cpsr & PSR_T_BIT) >> (__ffs(PSR_T_BIT))))
45 ((regs)->ARM_cpsr & MODE_MASK)
48 (!((regs)->ARM_cpsr & PSR_I_BIT))
51 (!((regs)->ARM_cpsr & PSR_F_BIT))
59 unsigned long mode = regs->ARM_cpsr & MODE_MASK; in valid_user_regs()
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/Linux-v6.1/arch/arm/mach-s3c/
Dirq-s3c24xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2003-2004 Simtec Electronics
30 #include "regs-irq.h"
31 #include "regs-gpio.h"
34 #include "regs-irqtype.h"
61 * @irqs irq-data, always s3c_irq_data[32]
83 struct s3c_irq_intc *intc = irq_data->intc; in s3c_irq_mask()
84 struct s3c_irq_intc *parent_intc = intc->parent; in s3c_irq_mask()
89 mask = readl_relaxed(intc->reg_mask); in s3c_irq_mask()
90 mask |= (1UL << irq_data->offset); in s3c_irq_mask()
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/Linux-v6.1/arch/arm/mm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
17 A 32-bit RISC microprocessor based on the ARM7 processor core
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
69 A 32-bit RISC microprocessor based on the ARM9 processor core
182 ARM940T is a member of the ARM9TDMI family of general-
184 instruction and 4KB data cases, each with a 4-word line
190 # ARM946E-S
201 ARM946E-S is a member of the ARM9E-S family of high-
202 performance, 32-bit system-on-chip processor solutions.
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/Linux-v6.1/arch/arm/kernel/
Dsetup.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 1995-2001 Russell King
46 #include <asm/mach-types.h>
147 u32 fiq[4]; member
307 /* I-cache aliases will be handled by D-cache aliasing code */ in cpu_has_aliasing_icache()
360 * These functions re-use the assembly code in head.S, which
520 * cpu_init - initialise one CPU.
522 * cpu_init sets up the per-CPU stacks.
545 * In Thumb-2, msr with an immediate value is not allowed. in cpu_init()
556 * setup stacks for re-entrant exception handlers in cpu_init()
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