1 // SPDX-License-Identifier: GPL-2.0
6  * Based on arch/arm/mach-ixp4xx/common.c
8  * Copyright 2003-2004 (C) MontaVista, Software, Inc.
28 #define IXP4XX_ICLR	0x08 /* Interrupt IRQ/FIQ Select */
30 #define IXP4XX_ICFP	0x10 /* FIQ Status */
33 #define IXP4XX_ICFH	0x1C /* FIQ Highest Pri Int */
35 /* IXP43x and IXP46x-only */
38 #define	IXP4XX_ICLR2	0x28 /* Interrupt IRQ/FIQ Select 2 */
40 #define IXP4XX_ICFP2	0x30 /* FIQ Status */
44  * struct ixp4xx_irq - state container for the Faraday IRQ controller
68 		return -EINVAL;  in ixp4xx_set_irq_type()
77 	if (ixi->is_356 && d->hwirq >= 32) {  in ixp4xx_irq_mask()
78 		val = __raw_readl(ixi->irqbase + IXP4XX_ICMR2);  in ixp4xx_irq_mask()
79 		val &= ~BIT(d->hwirq - 32);  in ixp4xx_irq_mask()
80 		__raw_writel(val, ixi->irqbase + IXP4XX_ICMR2);  in ixp4xx_irq_mask()
82 		val = __raw_readl(ixi->irqbase + IXP4XX_ICMR);  in ixp4xx_irq_mask()
83 		val &= ~BIT(d->hwirq);  in ixp4xx_irq_mask()
84 		__raw_writel(val, ixi->irqbase + IXP4XX_ICMR);  in ixp4xx_irq_mask()
97 	if (ixi->is_356 && d->hwirq >= 32) {  in ixp4xx_irq_unmask()
98 		val = __raw_readl(ixi->irqbase + IXP4XX_ICMR2);  in ixp4xx_irq_unmask()
99 		val |= BIT(d->hwirq - 32);  in ixp4xx_irq_unmask()
100 		__raw_writel(val, ixi->irqbase + IXP4XX_ICMR2);  in ixp4xx_irq_unmask()
102 		val = __raw_readl(ixi->irqbase + IXP4XX_ICMR);  in ixp4xx_irq_unmask()
103 		val |= BIT(d->hwirq);  in ixp4xx_irq_unmask()
104 		__raw_writel(val, ixi->irqbase + IXP4XX_ICMR);  in ixp4xx_irq_unmask()
115 	status = __raw_readl(ixi->irqbase + IXP4XX_ICIP);  in ixp4xx_handle_irq()
117 		generic_handle_domain_irq(ixi->domain, i);  in ixp4xx_handle_irq()
122 	if (ixi->is_356) {  in ixp4xx_handle_irq()
123 		status = __raw_readl(ixi->irqbase + IXP4XX_ICIP2);  in ixp4xx_handle_irq()
125 			generic_handle_domain_irq(ixi->domain, i + 32);  in ixp4xx_handle_irq()
135 	if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) {  in ixp4xx_irq_domain_translate()
136 		*hwirq = fwspec->param[0];  in ixp4xx_irq_domain_translate()
137 		*type = fwspec->param[1];  in ixp4xx_irq_domain_translate()
141 	if (is_fwnode_irqchip(fwspec->fwnode)) {  in ixp4xx_irq_domain_translate()
142 		if (fwspec->param_count != 2)  in ixp4xx_irq_domain_translate()
143 			return -EINVAL;  in ixp4xx_irq_domain_translate()
144 		*hwirq = fwspec->param[0];  in ixp4xx_irq_domain_translate()
145 		*type = fwspec->param[1];  in ixp4xx_irq_domain_translate()
150 	return -EINVAL;  in ixp4xx_irq_domain_translate()
157 	struct ixp4xx_irq *ixi = d->host_data;  in ixp4xx_irq_domain_alloc()
178 				    &ixi->irqchip,  in ixp4xx_irq_domain_alloc()
199  * ixp4x_irq_setup() - Common setup code for the IXP4xx interrupt controller
212 	ixi->irqbase = irqbase;  in ixp4xx_irq_setup()
213 	ixi->is_356 = is_356;  in ixp4xx_irq_setup()
215 	/* Route all sources to IRQ instead of FIQ */  in ixp4xx_irq_setup()
216 	__raw_writel(0x0, ixi->irqbase + IXP4XX_ICLR);  in ixp4xx_irq_setup()
219 	__raw_writel(0x0, ixi->irqbase + IXP4XX_ICMR);  in ixp4xx_irq_setup()
222 		/* Route upper 32 sources to IRQ instead of FIQ */  in ixp4xx_irq_setup()
223 		__raw_writel(0x0, ixi->irqbase + IXP4XX_ICLR2);  in ixp4xx_irq_setup()
226 		__raw_writel(0x0, ixi->irqbase + IXP4XX_ICMR2);  in ixp4xx_irq_setup()
233 	ixi->irqchip.name = "IXP4xx";  in ixp4xx_irq_setup()
234 	ixi->irqchip.irq_mask = ixp4xx_irq_mask;  in ixp4xx_irq_setup()
235 	ixi->irqchip.irq_unmask	= ixp4xx_irq_unmask;  in ixp4xx_irq_setup()
236 	ixi->irqchip.irq_set_type = ixp4xx_set_irq_type;  in ixp4xx_irq_setup()
238 	ixi->domain = irq_domain_create_linear(fwnode, nr_irqs,  in ixp4xx_irq_setup()
241 	if (!ixi->domain) {  in ixp4xx_irq_setup()
243 		return -ENODEV;  in ixp4xx_irq_setup()
263 		return -ENODEV;  in ixp4xx_of_init_irq()
268 	is_356 = of_device_is_compatible(np, "intel,ixp43x-interrupt") ||  in ixp4xx_of_init_irq()
269 		of_device_is_compatible(np, "intel,ixp45x-interrupt") ||  in ixp4xx_of_init_irq()
270 		of_device_is_compatible(np, "intel,ixp46x-interrupt");  in ixp4xx_of_init_irq()
278 IRQCHIP_DECLARE(ixp42x, "intel,ixp42x-interrupt",
280 IRQCHIP_DECLARE(ixp43x, "intel,ixp43x-interrupt",
282 IRQCHIP_DECLARE(ixp45x, "intel,ixp45x-interrupt",
284 IRQCHIP_DECLARE(ixp46x, "intel,ixp46x-interrupt",