| /Linux-v5.15/drivers/memory/samsung/ |
| D | exynos5422-dmc.c | 104 * Covers frequency and voltage settings of the DMC operating mode.
112 * struct exynos5_dmc - main structure describing DMC device
113 * @dev: DMC device
238 static int exynos5_counters_set_event(struct exynos5_dmc *dmc) in exynos5_counters_set_event() argument
242 for (i = 0; i < dmc->num_counters; i++) { in exynos5_counters_set_event()
243 if (!dmc->counter[i]) in exynos5_counters_set_event()
245 ret = devfreq_event_set_event(dmc->counter[i]); in exynos5_counters_set_event()
252 static int exynos5_counters_enable_edev(struct exynos5_dmc *dmc) in exynos5_counters_enable_edev() argument
256 for (i = 0; i < dmc->num_counters; i++) { in exynos5_counters_enable_edev()
257 if (!dmc->counter[i]) in exynos5_counters_enable_edev()
[all …]
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| D | Kconfig | 17 This adds driver for Exynos5422 DMC (Dynamic Memory Controller).
19 DMC and DRAM. It also supports changing timings of DRAM running with
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| D | Makefile | 2 obj-$(CONFIG_EXYNOS5422_DMC) += exynos5422-dmc.o
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| /Linux-v5.15/drivers/gpu/drm/i915/display/ |
| D | intel_dmc.c | 33 * DOC: DMC Firmware Support
35 * From gen9 onwards we have newly added DMC (Display microcontroller) in display
101 /* 0x09 for DMC */
104 /* Includes the DMC specific header in dwords */
119 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
161 /* DMC container header length in dwords */
177 /* DMC binary header length */
217 /* DMC RAM start MMIO address */
242 return i915->dmc.dmc_info[DMC_FW_MAIN].payload; in intel_dmc_has_payload()
278 * DMC firmware is read from a .bin file and kept in internal memory one time.
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| D | intel_display_power.c | 398 * - a DMC request on PW1 and MISC_IO power wells via the BIOS and in hsw_wait_for_power_well_disable()
711 * On GEN9 big core due to a DMC bug the driver's request bits for PW1 in hsw_power_well_enabled()
776 * doesn't stick and dmc keeps returning old value. Make sure in gen9_write_dc_state()
835 dev_priv->dmc.dc_state, val); in gen9_sanitize_dc_state()
836 dev_priv->dmc.dc_state = val; in gen9_sanitize_dc_state()
848 * Signal to DMC firmware/HW the target DC power state passed in @state.
849 * DMC/HW can turn off individual display clocks and power rails when entering
871 state & ~dev_priv->dmc.allowed_dc_mask)) in gen9_set_dc_state()
872 state &= dev_priv->dmc.allowed_dc_mask; in gen9_set_dc_state()
879 /* Check if DMC is ignoring our DC state requests */ in gen9_set_dc_state()
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| D | intel_display_debugfs.c | 535 struct intel_dmc *dmc; in i915_dmc_info() local
541 dmc = &dev_priv->dmc; in i915_dmc_info()
546 seq_printf(m, "path: %s\n", dmc->fw_path); in i915_dmc_info()
549 seq_printf(m, "Pipe A fw loaded: %s\n", yesno(dmc->dmc_info[DMC_FW_PIPEA].payload)); in i915_dmc_info()
551 seq_printf(m, "Pipe B fw loaded: %s\n", yesno(dmc->dmc_info[DMC_FW_PIPEB].payload)); in i915_dmc_info()
556 seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version), in i915_dmc_info()
557 DMC_VERSION_MINOR(dmc->version)); in i915_dmc_info()
569 * According to B.Specs:49196 DMC f/w reuses DC5/6 counter in i915_dmc_info()
571 * but TGL DMC f/w is using DMC_DEBUG3 reg for DC3CO counter. in i915_dmc_info()
590 intel_de_read(dev_priv, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); in i915_dmc_info()
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| /Linux-v5.15/Documentation/devicetree/bindings/edac/ |
| D | dmc-520.yaml | 4 $id: http://devicetree.org/schemas/edac/dmc-520.yaml#
7 title: ARM DMC-520 EDAC bindings
13 DMC-520 node is defined to describe DRAM error detection and correction.
20 - const: brcm,dmc-520
21 - const: arm,dmc-520
56 dmc0: dmc@200000 {
57 compatible = "brcm,dmc-520", "arm,dmc-520";
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| /Linux-v5.15/Documentation/admin-guide/perf/ |
| D | thunderx2-pmu.rst | 6 PMUs such as the Level 3 Cache (L3C), DDR4 Memory Controller (DMC) and
9 The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles.
13 The DMC and L3C support up to 4 counters, while the CCPI2 supports up to 8
16 overflow interrupt. DMC and L3C counters are 32-bit and read every 2 seconds.
21 The thunderx2_pmu driver registers per-socket perf PMUs for the DMC and
22 L3C devices. Each PMU can be used to count up to 4 (DMC/L3C) or up to 8
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| /Linux-v5.15/Documentation/devicetree/bindings/memory-controllers/ |
| D | samsung,exynos5422-dmc.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/samsung,exynos5422-dmc.yaml#
16 The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the
22 switch the DMC and memory frequency.
27 - const: samsung,exynos5422-dmc
60 - description: DMC internal performance event counters in DREX0
61 - description: DMC internal performance event counters in DREX1
110 compatible = "samsung,exynos5422-dmc";
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| /Linux-v5.15/Documentation/devicetree/bindings/devfreq/ |
| D | rk3399_dmc.txt | 1 * Rockchip rk3399 DMC (Dynamic Memory Controller) device
4 - compatible: Must be "rockchip,rk3399-dmc".
13 - center-supply: DMC supply node.
173 dmc: dmc {
174 compatible = "rockchip,rk3399-dmc";
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| D | exynos-bus.txt | 69 VDD_MIF |--- DMC
84 VDD_INT |--- DMC (parent device)
101 VDD_MIF |--- DMC
157 : VDD_MIF |--- DMC (Dynamic Memory Controller)
201 The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi
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| /Linux-v5.15/drivers/net/ethernet/sun/ |
| D | niu.h | 19 #define DMC 0x600000UL macro
1978 #define RXDMA_CFIG1(IDX) (DMC + 0x00000UL + (IDX) * 0x200UL)
1984 #define RXDMA_CFIG2(IDX) (DMC + 0x00008UL + (IDX) * 0x200UL)
1990 #define RBR_CFIG_A(IDX) (DMC + 0x00010UL + (IDX) * 0x200UL)
1996 #define RBR_CFIG_B(IDX) (DMC + 0x00018UL + (IDX) * 0x200UL)
2026 #define RBR_KICK(IDX) (DMC + 0x00020UL + (IDX) * 0x200UL)
2029 #define RBR_STAT(IDX) (DMC + 0x00028UL + (IDX) * 0x200UL)
2032 #define RBR_HDH(IDX) (DMC + 0x00030UL + (IDX) * 0x200UL)
2035 #define RBR_HDL(IDX) (DMC + 0x00038UL + (IDX) * 0x200UL)
2038 #define RCRCFIG_A(IDX) (DMC + 0x00040UL + (IDX) * 0x200UL)
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| /Linux-v5.15/drivers/perf/ |
| D | Kconfig | 116 in the DDR4 Memory Controller (DMC).
134 tristate "Enable PMU support for the ARM DMC-620 memory controller"
137 Support for PMU events monitoring on the ARM DMC-620 memory
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| D | arm_dmc620_pmu.c | 3 * ARM DMC-620 memory controller PMU driver
40 * The PMU registers start at 0xA00 in the DMC-620 memory map, and these
493 * DMC 620 PMUs are shared across all cpus and cannot in dmc620_pmu_event_init()
747 MODULE_DESCRIPTION("Perf driver for the ARM DMC-620 memory controller");
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| D | thunderx2_pmu.c | 13 /* Each ThunderX2(TX2) Socket has a L3C and DMC UNCORE PMU device.
60 /* DMC event IDs */
87 * Each socket has 3 uncore devices associated with a PMU. The DMC and
493 /* DMC event data_transfers granularity is 16 Bytes, convert it to 64 */ in tx2_uncore_event_update()
498 /* L3C and DMC has 16 and 8 interleave channels respectively. in tx2_uncore_event_update()
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| /Linux-v5.15/drivers/cpufreq/ |
| D | s5pv210-cpufreq.c | 194 * ch: DMC port number 0 or 1
207 pr_err("Cannot find DMC port\n"); in s5pv210_set_refresh()
536 /* Find current refresh counter and frequency each DMC */ in s5pv210_cpu_init()
599 * and DMC controller registers directly and remove static mappings in s5pv210_cpufreq_probe()
632 for_each_compatible_node(np, NULL, "samsung,s5pv210-dmc") { in s5pv210_cpufreq_probe()
633 id = of_alias_get_id(np, "dmc"); in s5pv210_cpufreq_probe()
635 dev_err(dev, "failed to get alias of dmc node '%pOFn'\n", np); in s5pv210_cpufreq_probe()
643 dev_err(dev, "failed to map dmc%d registers\n", id); in s5pv210_cpufreq_probe()
652 dev_err(dev, "failed to find dmc%d node\n", id); in s5pv210_cpufreq_probe()
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| /Linux-v5.15/drivers/soc/amlogic/ |
| D | meson-secure-pwrc.c | 100 /* DMC is for DDR PHY ana/dig and DMC, and should be always on */
101 SEC_PD(DMC, GENPD_FLAG_ALWAYS_ON),
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| /Linux-v5.15/drivers/edac/ |
| D | dmc520_edac.c | 4 * EDAC driver for DMC-520 memory controller.
25 /* DMC-520 registers */
43 /* DMC-520 types, masks and bitfields */
634 { .compatible = "arm,dmc-520", },
655 MODULE_DESCRIPTION("DMC-520 ECC driver");
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| D | Kconfig | 536 tristate "ARM DMC-520 ECC"
540 SoCs with ARM DMC-520 DRAM controller.
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| /Linux-v5.15/drivers/devfreq/ |
| D | Kconfig | 124 tristate "ARM RK3399 DMC DEVFREQ Driver"
131 This adds the DEVFREQ driver for the RK3399 DMC(Dynamic Memory Controller).
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| /Linux-v5.15/Documentation/gpu/ |
| D | i915.rst | 213 DMC Firmware Support
217 :doc: DMC Firmware Support
482 display microcontroller (DMC). The driver is responsible for loading the
484 to WOPCM using the DMA engine, while the DMC firmware is written through MMIO.
553 DMC section in Microcontrollers
555 See `DMC Firmware Support`_
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| D | meson.rst | 16 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
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| /Linux-v5.15/Documentation/devicetree/bindings/interrupt-controller/ |
| D | rda,8810pl-intc.txt | 39 21: DMC
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| /Linux-v5.15/Documentation/devicetree/bindings/clock/ |
| D | samsung,exynos-clock.yaml | 24 - samsung,exynos3250-cmu-dmc
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| /Linux-v5.15/arch/arm/boot/dts/ |
| D | s5pv210.dtsi | 512 dmc0: dmc@f0000000 {
513 compatible = "samsung,s5pv210-dmc";
517 dmc1: dmc@f1400000 {
518 compatible = "samsung,s5pv210-dmc";
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