398 	 * - a DMC request on PW1 and MISC_IO power wells via the BIOS and  in hsw_wait_for_power_well_disable()
711 	 * On GEN9 big core due to a DMC bug the driver's request bits for PW1  in hsw_power_well_enabled()
776 	 * doesn't stick and dmc keeps returning old value. Make sure  in gen9_write_dc_state()
835 		    dev_priv->dmc.dc_state, val);  in gen9_sanitize_dc_state()
836 	dev_priv->dmc.dc_state = val;  in gen9_sanitize_dc_state()
848  * Signal to DMC firmware/HW the target DC power state passed in @state.
849  * DMC/HW can turn off individual display clocks and power rails when entering
871 			     state & ~dev_priv->dmc.allowed_dc_mask))  in gen9_set_dc_state()
872 		state &= dev_priv->dmc.allowed_dc_mask;  in gen9_set_dc_state()
879 	/* Check if DMC is ignoring our DC state requests */  in gen9_set_dc_state()
880 	if ((val & mask) != dev_priv->dmc.dc_state)  in gen9_set_dc_state()
882 			dev_priv->dmc.dc_state, val & mask);  in gen9_set_dc_state()
889 	dev_priv->dmc.dc_state = val & mask;  in gen9_set_dc_state()
908 		if (dev_priv->dmc.allowed_dc_mask & target_dc_state)  in sanitize_target_dc_state()
968 				     DMC_PROGRAM(dev_priv->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),  in assert_dmc_loaded()
969 				     "DMC program storage start is NULL\n");  in assert_dmc_loaded()
971 		      "DMC SSP Base Not fine\n");  in assert_dmc_loaded()
973 		      "DMC HTP Not fine\n");  in assert_dmc_loaded()
1023 	if (state == dev_priv->dmc.target_dc_state)  in intel_display_power_set_target_dc_state()
1035 	dev_priv->dmc.target_dc_state = state;  in intel_display_power_set_target_dc_state()
1188 	if (dev_priv->dmc.target_dc_state == DC_STATE_EN_DC3CO) {  in gen9_disable_dc_states()
1211 		 * DMC retains HW context only for port A, the other combo  in gen9_disable_dc_states()
1230 	switch (dev_priv->dmc.target_dc_state) {  in gen9_dc_off_power_well_disable()
2746  * ICL PW_0/PG_0 domains (HW/DMC control):
2751  * ICL PW_1/PG_1 domains (HW/DMC control):
2963  * RKL PW_1/PG_1 domains (under HW/DMC control):
2970  * RKL PW_0/PG_0 domains (under HW/DMC control):
3085  * XELPD PW_1/PG_1 domains (under HW/DMC control):
3090  * XELPD PW_0/PW_1 domains (under HW/DMC control):
3411 		/* Handled by the DMC firmware */
3424 		/* Handled by the DMC firmware */
3505 		/* Handled by the DMC firmware */
3565 		/* Handled by the DMC firmware */
3713 		/* Handled by the DMC firmware */
4031 		/* Handled by the DMC firmware */
4366 		/* Handled by the DMC firmware */
4500 		/* Handled by the DMC firmware */
4659 		/* Handled by the DMC firmware */
5000 	 * not depending on the DMC firmware. It's needed by system  in get_allowed_dc_mask()
5111 	dev_priv->dmc.allowed_dc_mask =  in intel_power_domains_init()
5114 	dev_priv->dmc.target_dc_state =  in intel_power_domains_init()
5623 	 * may stay enabled after this due to DMC's own request on it.  in skl_display_core_uninit()
5686 	 * may stay enabled after this due to DMC's own request on it.  in bxt_display_core_uninit()
6178 	 * In case of suspend-to-idle (aka S0ix) on a DMC platform without DC9  in intel_power_domains_suspend()
6180 	 * DMC firmware will stay active, it will power down any HW  in intel_power_domains_suspend()
6184 	if (!(i915->dmc.allowed_dc_mask & DC_STATE_EN_DC9) &&  in intel_power_domains_suspend()
6375 			if (i915->dmc.allowed_dc_mask &  in intel_display_power_resume()
6378 			else if (i915->dmc.allowed_dc_mask &  in intel_display_power_resume()
6386 		    (i915->dmc.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))  in intel_display_power_resume()