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/Linux-v5.10/Documentation/devicetree/bindings/arm/
Dscu.txt3 As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
9 - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
11 - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
13 - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
16 - compatible : Should be:
17 "arm,cortex-a9-scu"
18 "arm,cortex-a5-scu"
19 "arm,arm11mp-scu"
21 - reg : Specify the base address and the size of the SCU register window.
26 compatible = "arm,cortex-a9-scu";
/Linux-v5.10/arch/arm/boot/dts/
Dowl-s500.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright (c) 2016-2017 Andreas Färber
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/power/owl-s500-powergate.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
24 #address-cells = <1>;
25 #size-cells = <0>;
29 compatible = "arm,cortex-a9";
[all …]
Dhighbank.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
6 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a9";
25 next-level-cache = <&L2>;
27 clock-names = "cpu";
[all …]
Darm-realview-eb-a9mp.dts23 /dts-v1/;
24 #include "arm-realview-eb-mp.dtsi"
27 model = "ARM RealView EB Cortex A9 MPCore";
30 * This is the Cortex A9 MPCore tile used with the
34 #address-cells = <1>;
35 #size-cells = <0>;
36 enable-method = "arm,realview-smp";
40 compatible = "arm,cortex-a9";
42 next-level-cache = <&L2>;
47 compatible = "arm,cortex-a9";
[all …]
Darm-realview-pbx-a9.dts23 /dts-v1/;
24 #include "arm-realview-pbx.dtsi"
28 * This is the RealView Platform Baseboard Explore for Cortex-A9
31 model = "ARM RealView Platform Baseboard Explore for Cortex-A9";
35 #address-cells = <1>;
36 #size-cells = <0>;
37 enable-method = "arm,realview-smp";
39 cpu-map {
51 compatible = "arm,cortex-a9";
53 next-level-cache = <&L2>;
[all …]
Dvexpress-v2p-ca9.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A9 MPCore (V2P-CA9)
8 * HBI-0191B
11 /dts-v1/;
12 #include "vexpress-v2m.dtsi"
15 model = "V2P-CA9";
18 compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <1>;
21 #size-cells = <1>;
[all …]
Dbcm63138.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 interrupt-parent = <&gic>;
22 #address-cells = <1>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-a9";
28 next-level-cache = <&L2>;
[all …]
Dnuvoton-npcm750.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include "nuvoton-common-npcm7xx.dtsi"
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&gic>;
13 #address-cells = <1>;
14 #size-cells = <0>;
15 enable-method = "nuvoton,npcm750-smp";
19 compatible = "arm,cortex-a9";
21 clock-names = "clk_cpu";
[all …]
Dtango4-smp8758.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include "tango4-common.dtsi"
6 #address-cells = <1>;
7 #size-cells = <0>;
8 enable-method = "sigma,tango4-smp";
11 compatible = "arm,cortex-a9";
12 next-level-cache = <&l2cc>;
16 clock-latency = <1>;
20 compatible = "arm,cortex-a9";
21 next-level-cache = <&l2cc>;
[all …]
Dzx296702.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/zx296702-clock.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
13 enable-method = "zte,zx296702-smp";
16 compatible = "arm,cortex-a9";
18 next-level-cache = <&l2cc>;
[all …]
Dspear13xx.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #address-cells = <1>;
10 #size-cells = <1>;
11 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "arm,cortex-a9";
21 next-level-cache = <&L2>;
25 compatible = "arm,cortex-a9";
28 next-level-cache = <&L2>;
[all …]
Dvf500.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a5";
28 intc: interrupt-controller@40003000 {
29 compatible = "arm,cortex-a9-gic";
30 #interrupt-cells = <3>;
[all …]
Dbcm-hr2.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
39 interrupt-parent = <&gic>;
40 #address-cells = <1>;
41 #size-cells = <1>;
44 #address-cells = <1>;
45 #size-cells = <0>;
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
56 compatible = "arm,cortex-a9-pmu";
[all …]
/Linux-v5.10/arch/arm/mach-prima2/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
21 bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform"
25 Support for CSR SiRFSoC ARM Cortex A9 Platform
28 bool "CSR SiRFSoC ATLAS7 ARM Cortex A7 Platform"
34 Support for CSR SiRFSoC ARM Cortex A7 Platform
37 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
43 Support for CSR SiRFSoC ARM Cortex A9 Platform
/Linux-v5.10/Documentation/devicetree/bindings/timer/
Darm,twd.txt3 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
4 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
7 The TWD is usually attached to a GIC to deliver its two per-processor
12 - compatible : Should be one of:
13 "arm,cortex-a9-twd-timer"
14 "arm,cortex-a5-twd-timer"
15 "arm,arm11mp-twd-timer"
17 - interrupts : One interrupt to each core
19 - reg : Specify the base address and the size of the TWD timer
24 - always-on : a boolean property. If present, the timer is powered through
[all …]
Darm,global_timer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stuart Menefy <stuart.menefy@st.com>
13 Cortex-A9 are often associated with a per-core Global timer.
18 - enum:
19 - arm,cortex-a5-global-timer
20 - arm,cortex-a9-global-timer
34 - compatible
35 - reg
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/arm/cpu-enable-method/
Dnuvoton,npcm750-smp2 Secondary CPU enable-method "nuvoton,npcm750-smp" binding
5 To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
8 Enable method name: "nuvoton,npcm750-smp"
10 Compatible CPUs: "arm,cortex-a9"
14 This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
15 "nuvoton,npcm750-gcr".
20 #address-cells = <1>;
21 #size-cells = <0>;
22 enable-method = "nuvoton,npcm750-smp";
26 compatible = "arm,cortex-a9";
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/cpufreq/
Dcpufreq-dt.txt11 - None
14 - operating-points: Refer to Documentation/devicetree/bindings/opp/opp.txt for
17 - clock-latency: Specify the possible maximum transition latency for clock,
19 - voltage-tolerance: Specify the CPU voltage tolerance in percentage.
20 - #cooling-cells:
22 Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml.
27 #address-cells = <1>;
28 #size-cells = <0>;
31 compatible = "arm,cortex-a9";
33 next-level-cache = <&L2>;
[all …]
/Linux-v5.10/arch/arm/mach-bcm/
Dbcm63xx_smp.c1 // SPDX-License-Identifier: GPL-2.0-only
22 /* Size of mapped Cortex A9 SCU address space */
26 * Enable the Cortex A9 Snoop Control Unit
29 * cores present. We assume we're running on a Cortex A9 processor,
43 return -ENXIO; in scu_a9_enable()
50 return -ENOENT; in scu_a9_enable()
57 return -ENOMEM; in scu_a9_enable()
70 /* The BCM63138 SoC has two Cortex-A9 CPUs, CPU0 features a complete in scu_a9_enable()
72 * Since we will not be able to trap kernel-mode NEON to force in scu_a9_enable()
76 * all, for kernel-mode NEON, we do not want to introduce any in scu_a9_enable()
[all …]
/Linux-v5.10/arch/arm/mach-vexpress/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
24 This option enables support for systems using Cortex processor based
28 - CoreTile Express A5x2 (V2P-CA5s)
29 - CoreTile Express A9x4 (V2P-CA9)
30 - CoreTile Express A15x2 (V2P-CA15)
31 - LogicTile Express 13MG (V2F-2XV6) with A5, A7, A9 or A15 SMMs
33 - Versatile Express RTSMs (Models)
42 bool "Enable A5 and A9 only errata work-arounds"
49 based on Cortex-A5 and Cortex-A9 processors. In order to
68 between the dual cluster test-chip and the M3 microcontroller that
/Linux-v5.10/Documentation/devicetree/bindings/arm/ux500/
Dboards.txt1 ST-Ericsson Ux500 boards
2 ------------------------
5 compatible = "st-ericsson,mop500" (legacy)
6 compatible = "st-ericsson,u8500"
10 soc: represents the system-on-chip and contains the chip
20 compatible = "ste,dbx500-backupram"
25 interrupt-controller:
26 see binding for interrupt-controller/arm,gic.txt
36 /dts-v1/;
39 model = "ST-Ericsson HREF (pre-v60) and ST UIB";
[all …]
/Linux-v5.10/arch/arm/mach-realview/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
34 the ARM926EJ-S core tile, while on an ARMv6/v7 kernel, at least
35 one of the ARM1136, ARM1176, ARM11MPCore or Cortex-A9MPCore
39 bool "Support ARM1136J(F)-S Tile"
47 bool "Support ARM1176JZ(F)-S Tile"
54 bool "Support Multicore Cortex-A9 Tile"
57 Enable support for the Cortex-A9MPCore tile fitted to the
74 the ARM11MPCore. This platform has an on-board ARM11MPCore and has
75 support for PCI-E and Compact Flash.
79 bool "Support RealView(R) Platform Baseboard for ARM1176JZF-S"
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/interrupt-controller/
Darm,gic.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
29 - arm,arm11mp-gic
30 - arm,cortex-a15-gic
[all …]
/Linux-v5.10/arch/arm/mach-zynq/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 bool "Xilinx Zynq ARM Cortex A9 Platform"
18 Support for Xilinx Zynq ARM Cortex A9 Platform
/Linux-v5.10/arch/arm/mach-artpec/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
9 bool "Axis ARTPEC-6 ARM Cortex A9 Platform"
20 Support for Axis ARTPEC-6 ARM Cortex A9 Platform

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